Abstract: There are several applications in VLSI technology that require high-speed shortest-path computations. The shortest path is a path between two nodes (or points) in a graph such that the sum of the weights of its constituent edges is minimum. Floyd-Warshall algorithm provides fastest computation of shortest path between all pair of nodes present in the graph. With rapid advances in VLSI technology, Field Programmable Gate Arrays (FPGAs) are receiving the attention of the Parallel and High Performance Computing community. This paper gives implementation outcome of Floyd-Warshall algorithm to solve the all pairs shortest-paths problem for directed graph in Verilog

Ajay Somkuwar

Sachin Awasthi

Vijayshri Chaurasia

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International Association of Scientific Innovation and Research (IASIR) 
(An Association Unifying the Sciences, Engineering, and Applied Research) 
 
               International Journal of Emerging Technologies in Computational 
and Applied Sciences (IJETCAS) 
www.iasir.net  
IJETCAS 13-218; © 2013, IJETCAS All Rights Reserved                                                                                                          Page 615 
 
ISSN (Print): 2279-0047  
ISSN (Online): 2279-0055 
 
Verilog Implementation of a System for Finding Shortest Path by Using 
Floyd-Warshall Algorithm 
1Sachin Awasthi, 
2Vijayshri Chaurasia, 
3Ajay Somkuwar  
Department of Electronics and Communication Engineering 
Maulana Azad National Institute of Technology, Bhopal 
    INDIA 
 
Abstract:  There  are  several  applications  in  VLSI  technology  that  require  high-speed  shortest-path 
computations. The shortest path is a path between two nodes (or points) in a graph such that the sum of the 
weights of its constituent edges is minimum. Floyd-Warshall algorithm provides fastest computation of shortest 
path  between  all  pair  of  nodes  present  in  the  graph.  With  rapid  advances  in  VLSI  technology,  Field 
Programmable  Gate  Arrays  (FPGAs)  are  receiving  the  attention  of  the  Parallel  and  High  Performance 
Computing community. This paper gives implementation outcome of Floyd-Warshall algorithm to solve the all 
pairs shortest-paths problem for directed graph in Verilog.  
 
Keywords:  shortest  path;  vertex;  all  pairs  shortest-paths;  Floyd-Warshall  algorithm  ;  FPGA;  Xilinx  ISE; 
Verilog; running efficiency. 
I.  Introduction 
In graph theory, the shortest path problem is the problem of computing a path between two vertices (or nodes) 
such that the sum of the weights of its constituent edges is minimized. Shortest path algorithms are applied to 
many  fields,  such  as  operations  research,  plant  and  facility  layout,  robotics,  transportation,  logistics,  VLSI 
design etc [2]. There are many shortest path finding algorithms: the most widely used are Dijkstra, Floyd-
warshall and bellman ford algorithms, all the three algorithms having different area of applications. For finding 
shortest path between any one pair of nodes in the graph Dijkstra algorithm is best suitable, for finding shortest 
path  from  one  node  to  remaining  all  other  nodes  in  a  graph  Bellman  Ford  algorithm  is  preferred  and  for 
computation of shortest path between all possible node pairs in the graph Floyd-Warshall algorithm (FWA) is 
fastest among all. The all-pairs shortest paths (APSP) problem is to find shortest paths between all-pairs of 
vertices in a weighted graph, and it is usually equivalent to make a table of minimum distances for every pair 
[3].  The  problem  is  one  of  the  most  fundamental  graph  problems.  We  can  find  applications  of  the  APSP 
problem  in  bioinformatics,  social  networking,  traffic  routing,  etc.  Moreover,  the  APSP  problem  can  be 
generalized to the  algebraic path problem [4-5]  which covers several basic graph problems.  A  well-known 
solution of the APSP problem is to apply FWA algorithm which requires       operations on       memory 
space, where     is the number of vertices in the graph.  
Applications of Shortest-path algorithm- 
• Maps 
• Robot navigation. 
• Texture mapping. 
• Urban traffic planning. 
• Optimal pipelining of VLSI chip. 
• Subroutine in advanced algorithms. 
• Telemarketer operator scheduling. 
• Routing of telecommunications messages. 
• Approximating piecewise linear functions. 
• Network routing protocols (OSPF, BGP, and RIP). 
• Exploiting arbitrage opportunities in currency exchange. 
• Optimal truck routing through given traffic congestion pattern. 
 
II.  Floyd-Warshall algorithm 
 
Floyd-Warshall algorithm is a dynamic programming formulation, to solve the all-pairs shortest path problem 
on  directed  graphs[1].  It  finds  shortest  path  between  all  nodes  in  a  graph.  The  algorithm  considers  the 
intermediate vertices of a simple path are any vertex present in that path other than the first and last vertex of S Awasthi et al.,  International Journal of Emerging Technologies in Computational and Applied Sciences,  4(6), March-May, 2013, pp.615-
620 
IJETCAS 13-218; © 2013, IJETCAS All Rights Reserved                                                                                                          Page 616 
 
that path. Before 1960 it was tough task to find all pair shortest path. Warshall was interested to determine 
shortest path between each pair of vertices u and v, whether u can reach v. The Floyd-Warshall algorithm is the 
improvement of this algorithm, running in O     time. The intelligence of the Floyd-Warshall algorithm is in 
finding a different formulation for the shortest path sub-problem than the path length formulation. At first the 
formulation may seem most unnatural, but it leads to a faster algorithm [9]. We will compute a set of matrices 
whose entries are     
   . We will change the meaning of each of these entries. For a path                  we 
say that the vertices                are the intermediate vertices of this path. Note that a path consisting of a 
single  edge  has  no  intermediate  vertices.  We  define     
    to  be  the  shortest  path  from   to   such  that  any 
intermediate vertices on the path are chosen from the set          . In other words, we consider a path from   
to   which either consists of the single edge     , or it visits some intermediate vertices along the way, but these 
intermediate vertices can only be chosen from          . The path is free to visit any subset of these vertices, 
and to do so in any order. Thus, the difference between Floyd’s formulation and the previous formulation is that 
the superscript     restricts the set of vertices that the path are allowed to pass through, and the superscript     
restricts the number of edges the path allowed to use. For example, in the digraph shown in figure 1, notice how 
the value of     
    changes as   varies. We compute     
    assuming that we have already computed the previous 
matrix      . As before, there are two basic cases, depending on the ways that we might get from vertex   to 
vertex , assuming that the intermediate vertices are chosen from             . 
Figure 1  
4
1
2
3
1
4
2
8
9 1
 
    
                        
    
                
    
                
    
                
    
                 
 
 
Any graph (directed or undirected)             where V is the no. of vertices and E is the no. of edges. with 
weight function          find for all pairs of vertices         the minimum possible weight for path from   to 
 .  
  Finding the shortest path between all pair of vertices in a graph. 
  For the general case negative edge is also allowed. The problem can be solved by running the Bellman-
Ford algorithm     times, once for each vertex as the source. 
Time complexity:          If the graph is dense:         
  The Floyd-Warshall algorithm solves the same problem in       
  Competitive for dense graph. 
  Use adjacency matrices, as opposed to adjacency list. 
  Let the vertices of   be             and consider         be a subset of vertices for some k. 
For any pair of vertices           consider all paths from   to   whose intermediate vertices are all drawn from 
        and  let   be  a  minimum  weight  path  among  them.  The  Floyd-Warshall  algorithm  exploits  a 
relationship between path   and a shortest path from   to   with all intermediate vertices in the set       . The 
relationship depends on whenever or not   is an intermediate vertex of . 
 
 
 
 
 S Awasthi et al.,  International Journal of Emerging Technologies in Computational and Applied Sciences,  4(6), March-May, 2013, pp.615-
620 
IJETCAS 13-218; © 2013, IJETCAS All Rights Reserved                                                                                                          Page 617 
 
Figure 2 graph showing intermediate path 
 
i j k
P
All intermediate vertices of {1,2,…..k} 
 
 
From figure 2 If   is not in , then the shortest path from   to   with all intermediate vertices in the set         
is also a shortest path in the set       . If   is in , then we break down   into    and    where, 
     is the shortest path from   to   with all intermediate vertices in the set          
     is the shortest path from   to   with all intermediate vertices in the set          
 
III.  Methodology 
 
The methodology of Floyd-Warshall algorithm to find all pairs shortest paths is as follow: 
 
Let           be a weighted directed graph with an edge-weight function          that assigns real-valued 
weights to edges, where             } is a set of   vertices, and           is a set of edges. We assume that 
there are no negative-weight cycles in a graph   though the presence of negative-weight edges is allowed. Let 
us use an adjacency matrix representation for a graph . The input of the all-pairs shortest paths problem is an 
       matrix              where        represents the edge weight from a vertex   to a vertex   in a graph   
with   vertices, i.e. 
 
 
          
                                                            
                                           
                                                        
                                                                ……………. (1) 
 
Let a path   be an arbitrary sequence of vertices. The distance of a path is the sum of lengths of all intermediate 
edges in the sequence of vertices. If we denote a set of paths from   to   with      , the shortest-path distance 
between any pair       of vertices can be defined as 
 
                                                                                                           …………….. (2) 
 
Where   is the number of intermediate vertices. Then, the all-pairs shortest paths (APSP) problem is to find an  
      matrix              for a given       matrix . We can define a recursive formulation to compute the 
shortest-path distances. Let       
      be the distance of a shortest path       in which all the intermediate vertices 
are in the set            the recurrence is defined as 
 
      
       
                                                                                                                            
                                                                                    
               .…………….(3) 
 
The matrix                gives an answer to the APSP problem, i.e.                  .  
 
 
 
 
IV.  Implementation and result 
The Floyd-Warshall algorithm is implemented in Verilog by using Xilinx-13.2. By using this we can find all 
pairs shortest path in any given graph having     no. of nodes. The simulation results are given by implementing 
it on graph shown in figure I. 
 
 S Awasthi et al.,  International Journal of Emerging Technologies in Computational and Applied Sciences,  4(6), March-May, 2013, pp.615-
620 
IJETCAS 13-218; © 2013, IJETCAS All Rights Reserved                                                                                                          Page 618 
 
 
Figure 3 Three node graph taken for testing of Floyd-Warshall algorithm 
1
2
3
4
3
1 1
6
1
 
 
The graph is having three nodes in which we have computed all pairs shortest path. There are two input matrix 
of size      , one is cost matrix and other is adjacency matrix. In the cost matrix the actual weight is written and 
in the adjacency matrix the connection is indicated whether the pair is connected or not. If connected then write 
    if not connected then    . Here one weight is indicated by three bits, so there will be maximum    bits.   
 
Figure 4 Top level schematic of Floyd-Warshall algorithm 
 
 
The top level schematic diagram of Floyd-Warshall generated through implementation in Verilog is shown in 
figure 4. It consists of six inputs and four outputs. The verilog has generated a pin diagram which defines input, 
output, and clock etc. The top level schematic in figure 4 consists of 10 pins each pin having its own working. 
Here input is taken as matrix i.e. adjacency matrix and cost matrix in adjacency matrix we define the direct 
connection between two nodes  whether these are connected or not and in cost matrix the actual  weight is 
written. The CLK pin is used to give clock. The EN_adjecency matrix and EN_cost matrix pin is given to enable 
the matrices for operation. RST pin is to reset the previous result. Here the output will be taken by the pin 
p(26:0) which is also in the matrix form. The final result obtained is shown in figure III. 
 
Figure 5 Input-output waveform by simulation in verilog 
 
 
 
     S Awasthi et al.,  International Journal of Emerging Technologies in Computational and Applied Sciences,  4(6), March-May, 2013, pp.615-
620 
IJETCAS 13-218; © 2013, IJETCAS All Rights Reserved                                                                                                          Page 619 
 
   Here the generated output  waveform showing the output of each pin of pin diagram shown in  figure II. 
Initially no input was there. After 400ns when input is applied in pin graph_in then corresponding output with 
clock will be generated this is shown in figure III.  
 
V.  Timing Detail 
While finding shortest path the timing is main aspect and it should be as low as possible. The time taken is 
directly proportional to the total no. of nodes there in the graph. Here we have taken   nodes graph and the 
timing detail of that graph is given below. All values are displayed in nanoseconds      
 
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK' 
Total number of paths / destination ports: 757 / 22 
Offset:              6.942ns (Levels of Logic = 5) 
 
In the graph we have to move from source to destination. Here the source is cost matrix and the destination is 
   . The total time is taken in the process is       . Here the table given below defines the separate time 
consume by each element and then total time. 
Some Look Up Tables are generated in the architecture the processing time of each LUT is given in the table I 
 
Table I Timing detail  
 
Gate     Net 
Cell: in->out      fanout   Delay              Logical Name (Net Name) 
IBUF: I->O             2        1.218     0.622 cost_matrix_y_4_IBUF (cost_matrix_y_4_IBUF) 
LUT3:I0->O            1       0.704     0.424 p_cmp_eq00011_SW0 (N5) 
LUT4:I3->O            2       0.704     0.622 p_cmp_eq00011 (N1) 
LUT3:I0->O            8       0.704     0.932 p_cmp_eq000130 (p_cmp_eq0001) 
LUT3:I0->O            1       0.704     0.000 p_mux0000<20>11 (p_mux0000<20>1) 
FDS: D                             0.308                p_6 
Total                      6.942ns (4.342ns logic, 2.600ns route)  
              (62.5% logic, 37.5% route) 
 
The table II gives the estimated value of Device Utilization. This table gives the total utilization of available 
devices i.e. no. of slices, no. of look-up tables (LUTs), and no. of input output buses and in terms of clock used 
with their % used 
Table II Device Utilization summary (estimated value) 
 
Logic utilization  Used  Available  % Utilization 
Number of slices  19  4656  0% 
Number of 4 input LUTs  33  9312  0% 
Number of bonded IOBs  100  232  43% 
Number of GCLKs  1  24  4% 
 
All pair shortest path may also be computed by Dijkstra and Bellman Ford algorithms but these algorithms are 
the slower than that of Floyd-Warshall algorithm. Dijkstra algorithm is very much useful for finding the shortest 
distance between any two nodes. If we want to find all pairs shortest paths than Dijkstra algorithm need to run 
separately for all possible pairs in the graph. This process will consume large time. The Bellman Ford algorithm 
is used to find the distance from one source to remaining node. To find all pairs shortest path by Bellman ford 
algorithm needs to run separately for all nodes present in the graph. The Floyd-Warshall algorithm is the fastest 
algorithm for computation all pair’s shortest paths in the graph, it provides all pairs shortest paths by running 
only once and is the fastest one.      
   
VI.  Conclusion  
In this paper we have presented implementation of Floyd-Warshall algorithm for finding all pairs shortest paths 
in Verilog. To find all pairs shortest paths the Dijkstra algorithm need to run separately for each possible pair 
this process consume more time and is the slowest process. The Bellman Ford algorithm needs to run for each 
node and the Floyd-Warshall algorithm will provide all pairs shortest paths by running only once and is the 
fastest algorithm. The Verilog is the Hardware Description Language which can be used to generate hardware 
for any code. Verilog codes for Floyd-Warshall algorithm can be further used to burn Field Programmable Gate 
Array (FPGA). Since FPGA based hardware for path solvers performs much faster  as compared to general 
purpose  processor.   The  Floyd-Warshall  algorithm  can  be  efficiently  applied  to  the  systems  of  large  node S Awasthi et al.,  International Journal of Emerging Technologies in Computational and Applied Sciences,  4(6), March-May, 2013, pp.615-
620 
IJETCAS 13-218; © 2013, IJETCAS All Rights Reserved                                                                                                          Page 620 
 
number and it leads to a significant improvement in running efficiency. Xilinx ISE design suit is used with 
device as SPARTEN3E XC3S250E for the work presented 
 
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