Design of Robust and Power Efficient Full Adder Using Energy Efficient Feed through Logic

Abstract

ABSTRACT – An Energy Efficient Feedthrough Logic (EE-FTL) is proposed in this paper to reduce the power consumption for low power applications. The EE-FTL is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. It has a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage are ready. The proposed logic style requires low power when compare to the existing feedthrough logic (FTL). The proposed circuit is simulated and a comparison analysis has been carried out using 90-nm, 1.2V CMOS process technology. A CMOS Full Adder is designed by the energy efficient feedthrough logic and the simulation result in MicroWind environment shows that the proposed logic reduces the power consumption by 77%, 70 % and 36 % over FTL, Low Power FTL (LP-FTL) and Constant Delay Logic (CDL), respectively. The problem of requirement of inverter as in dynamic logic is completely eliminated in the proposed logic