Power and Performance Optimization for De-synchronized Circuits

Abstract

design flow, power reduction, performance improvement, multiplier Abstract The de-synchronization methodology, which directly converts a synchronous circuit into an asynchronous counterpart according to the physical structure of pipelines, is very popular for its simplicity. However, the simplicity of the design methodology also introduces some power redundancy and performance reduction to de-synchronized circuits. This paper first investigates the influence of actual operations and operands to de-synchronized circuits, and then proposes an improved de-synchronization flow to resolve the power and performance problem in conventional de-synchronized circuits. At last, some specific schemes which are early completion, decoupling and delay element optimization are employed to optimize a traditional de-synchronized multiplier. Compared to a traditional de-synchronized multiplier, early completion can achieve as high as 72% power reduction and 54 % performance improvement. While the power saving resulting from decoupling is about 20%-25 % and performance improvement by optimizing delay elements is about 11%. 1