A New design using CLRCL Full Adder Logic in 180 nm Technology

Abstract

Abstract — This article explains a low complexity full adder design using 10 transistors having higher computing speed, lower operating voltage and lower energy consumption. The simulation results, based on 0.18um process models indicate that the proposed de sign has the lowest working Vdd and highest working frequency. Apart from this, the performance edge of the proposed design in terms of speed and energy consumption become even more significant as the word length of the adder increases