Analysis of MOS capacitor with p-layer with TCAD simulation

Abstract

The ATLAS18 strip sensors of the ATLAS inner tracker upgrade (ITk) are under production since 2021. Along with the large-format n^+-in-p strip sensor in the center of the wafer, test structures are laid out in the open space for monitoring the performance of the strip sensor and its fabrication process. One of the structures is a 1.2×1.0 mm^2 test chip that includes representative structures of the strips, and Metal-Oxide-Silicon (MOS) capacitors. In addition to the standard MOS capacitor, a MOS capacitor with a p-layer in the surface of silicon, the MOS-p capacitor, is designed with a p-density representative of the p-stop doping for isolating the n+ strips. The C-V curve of the MOS capacitor shows characteristic behavior in the accumulation, depletion, and inversion regions as a function of bias voltage, from which one can estimate the amount of the interface charge. The MOS-p capacitor shows the C-V curve modulated by the properties of the p-layer. With over 50% of the full production complement delivered, we have observed consistent characteristics in the MOS-p capacitors. Rarely and currently only in 3 batches, we have observed abnormalities. To further study them, we have simulated the MOS-p capacitor with TCAD software, which successfully reproduces the normal behavior, including a feature caused by a geometrical setback of the p-layer to the metal area, with the p-density and the interface charge within the expected range. By contrast, the overall shapes of the abnormal cases are only reproduced with 1/10 of the p-density to the specification and possible charge traps in the p-layer area. A smaller but distinctive feature in the behavior may require a non-uniform distribution of the p-density and the interface charge or something else. These simulations help to take final decisions for the batches in production