A dedicated analogue multiplexer chip (AMUX) for the readout of silicon strip detectors was designed and manufactured in 1.2µm n-well CMOS AMS technology

Kaplon, J

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EUROPEAN ORGANIZATION FOR NUCLEAR RESEARCHCERN/ECP 95-1108 June 1995FAST, LOW POWER, ANALOGUE MULTIPLEXER FOR READOUTOF MULTICHANNEL ELECTRONICSJan KAPLONCERNCH1211, Geneva 23, SwitzerlandABSTRACTA dedicated analogue multiplexer chip (AMUX) for the readout of silicon stripdetectors was designed and manufactured in 1.2 µm n-well CMOS AMS technology.Presented at the 2nd Advanced Training Course: MIXED DESIGN OF VLSICIRCUIT, KRAKOW, POLANDMay 29-31, 19951FAST, LOW POWER, ANALOGUE MULTIPLEXER FOR READOUTOF MULTICHANNEL ELECTRONICSJan KAPLONCERNCH1211, Geneva 23, SwitzerlandABSTRACTA dedicated analogue multiplexer chip (AMUX) for the readout of siliconstrip detectors was designed and manufactured in 1.2µm n-well CMOS AMStechnology.1. INTRODUCTIONSince in a particle physics experiment a very large number of sensors and readoutelectronics is placed in a small volume, low power consumption at a given speed is a drivingissue for the presented design. A huge number of electronic channels placed in a small volumerequires the use of low power techniques for building a fast analogue multiplexer. Our goalswere to design a 32 channel analogue multiplexer with the following parameters:– power dissipation less than 50mW for 32 channels,– readout speed 20MHz,– dynamic range at the input 0 ÷ 1V, power supply ±2V–maximum load capacitance 20pF, typical 10pF.2. THE ARCHITECTURE OF THE AMUX AND READOUT BUFFERThe schematic of the analogue multiplexer is shown on Fig. 1. The multiplexer chipcontains 32 input channels with sample-and-hold circuits. In addition to the 32 input channels,one extra channel is used to cancel the offset and the cross-talk from the digital part. Theoutput of this channel is used as a reference for the differential output. Each channel consists ofan input switch, a storage capacitor and an input buffer designed as a source follower based onan NMOS transistor biased with 20µA. Because of the n-well technology is used, the gain ofthis stage is about 0.8. The multiplexing function is implemented as a simple array of 32NMOS switches controlled by a shift register connected by analogue bus line to the outputbuffer. The parasitic capacitance of this line is about 4pF for 32 channels (including drain-bulkcapacitance of the switches) and therefore it is necessary to adapt the current in the readoutchannel. We can obtain this in a simple way by adding a pull-up NMOS transistor (working asa resistor) connected to the VSS. The value of this resistor together with the switch resistancelimits the output current and speed and also has influence on the linearity of the multiplexer.Assuming that transistors M3 and MP work in their linear region and M1 works in saturation wecan simply calculate the resistance of the switches and the readout current using the followingformulae:2                                          ( )R v i k wl v von ds dsgs t= ≅⋅  ⋅ −∂ ∂ 1                                   (1)                                                    i k wlv vd gs t≅ ⋅ ⋅ −22( )                                                  (2)INPUT 1OUTVCCHOLDHOLDCH.5pF180/1.260/584/1.2VSSBIAS, 20µΑΜ1Μ2Μ3Μ4 4/1.2Μ5 2/1.2Μ6 2/1.2READ BITINPUT 32VCCHOLDHOLDCH.5pF180/1.260/584/1.2VSSBIAS, 20µΑΜ1Μ2Μ3Μ4 4/1.2Μ5 2/1.2Μ6 2/1.2INPUT AUXVCCHOLDHOLDCH.5pF180/1.260/584/1.2VSSBIAS, 20µΑΜ1Μ2Μ3Μ4 4/1.2Μ5 2/1.2Μ6 2/1.2Q DCLKQ DCLKREAD CLK32 OUT AUXMP12/8VPMPVP12/8OUTPUT BUFFEROUTPUT BUFFERFig. 1. Schematic diagram of the multiplexer.Because the resistance of MP is about 4.1kΩ and the switch resistance is about 100Ω the smallnonlinearity which comes from the M3 switch (its resistance is a function of Uout) can beneglected. The current flowing in the readout channel is in the range of 300 ÷ 600µA for theinput voltage swing 0 ÷ 1V. It provides a slew rate not less than 75V/µs for line parasiticcapacitance of 4 pF. To obtain the assumed speed of the MUX of 20 MHz for a maximum loadcapacitance 20 pF an additional output buffer is required.The schematic diagram of the output buffer is shown in Fig. 2. The configuration usedin the circuit is based on the well known push-pull circuit. The push-pull CMOS invertingamplifier built with M1 and M2 transistors is controlled by two error amplifiers. The erroramplifiers biased with 300µA set the DC operating point and apply negative feedback to thegate of the common-source M1 and M2 transistors. For the transistor sizes given in Fig. 2 and3nominal power supply ±2 V, the current flowing through the transistors M1 and M2 is about 5mA. This provides an A class buffer which gives high linearity and low output resistance.BIASPINPUTBIASNM1M2OUTC1 1pFC21pFM3 M4M5M6M7M8 M9M10M11M12VSSVCC20/1.2 20/1.2660/1.250/1.2246.6/1.250/1.240/38.4/1.28.4/1.2120/1.2 120/1.290/3Fig. 2. Schematic diagram of the output buffer.(gm4+gm9)(Uout-Uin)gm6+gm10(gm3+gm8)(Uin-Uout)gds3+gds7+gds8+gds11C1+C2Ur(gm1+gm2)gds1+gds2Uin Ur UoutFig. 3. Simplified equivalent model of Fig. 2.The simplified equivalent model of the output buffer is shown in Fig. 3. Assuming thatthe transconductances gmi of the transistors used in the error amplifiers are the same and thetransconductances gmo of the output devices are the same, we can find the expressions for thegain and the output resistance. Using nodal analysis we can write:                                              ( )Uout ggggUin Uoutmidsimodso= ⋅⋅−2                                     (3)Solving for Uout/Uinp yields the gain of the buffer:                                                        A A AA A=⋅+ ⋅≅1 21 211                                                    (4)where A g gmi dsi1 2= ⋅  is the gain of the error amplifier and A g gmo dso2 =  is the gain of theoutput push-pull stage in open loop configuration. The small signal output resistance of thebuffer can be calculated from equation (5):4                                            i Ur g Uout gout mo dso= ⋅ ⋅ + ⋅ ⋅2 2                                            (5)Substituting equation (3) and (4) and solving equation (5) for Uout/Iout gives:                                                Routg A Adso=⋅⋅+ ⋅1212 1 2                                              (6)The output resistance of the buffer is the output resistance of the push-pull stage divided by theopen loop gain of the error amplifier and the output stage. For the given values the outputresistance is about 1Ω.The presented output buffer is a typical second-order circuit. The compensation of thebuffer is done by adding the C1, C2 Miller capacitors. The 5 mA current flowing through M1,M2 provides not only the low output resistance but also the high bandwidth which is our basicgoal. The unity-gain bandwidth can be shown to be approximately                                                          GB gC Cmi≅⋅+21 2                                                        (7)With regard to compensation, the goal was to achieve a phase margin equal to 60° for thenominal 10pF load capacitance. Assuming that the RHP zero is placed ten times higher thanGB the second pole must be placed 2.2 times higher than GB. The following relationshipapplies:                                                       210 21 2 1 2⋅+〉 ⋅ ⋅+gC CgC Cmo mi                                           (8a)Therefore,                                                                g gmo mi〉 ⋅10                                                       (8b)and furthermore                                                          2 2 2 21 2⋅ 〉 ⋅ ⋅+gCloadgC Cmo mi.                                               (9)Combining equations (8b) and (9) gives the requirement for the Miller C1, C2 capacitors:C C Cload1 2 0 22+ 〉 ⋅. . In our case the transconductance gmi and gmo are 935µS and 12mSrespectively. This allows a 60° phase margin for C1 = C2 = 1pF for 10pF load capacitance.3. LAYOUTThe 32 channels of the multiplexer were placed in 42.4µm pitch. These channels are separatedby the diffusion guardrings to cancel cross-talk between the neighbours. The presented designis a typical mixed analogue and digital circuit. A digital circuit is placed close to the analogcircuit. To avoid cross-talk between the analogue and digital parts the power supply isseparated. To decrease the coupling from the digital part through the substrate, the clock linesare placed symmetrically (clock and clock bar) over the POLY 1 layer connected externally tothe ground.54. RESULTSThe -3dB bandwidth of the buffer is equal to 115 MHz and the settling time for a 1V step atthe input is 25ns as shown in Fig. 4 and Fig. 5 respectively. A voltage gain of 0.75 ismeasured. and the power dissipated by the multiplexer is about 23mW. The output response ofthe multiplexer is presented in Fig. 5. The upper trace shows the output waveform measuredfor a readout clock of 20 MHz. The settling time for 1V step at the input is about 30ns whichshows that we have a good safety margin with respect to 20MHz operation. The channel offsetspread together with cross-talk from neighbour channel is less than 5mV as shown in Fig. 6. 5. CONCLUSIONAn analogue multiplexer for the serial readout of multichannel front end system forparticle detector has been presented. The design has been optimised to set a settling time lessthan 30ns with the nominal power consumption. For the nominal capacitive loads 20MHzreadout speed and 23mW power dissipation are obtained. The AMUX chip has already beenused in the test of silicon particle sensors and in the future will be implemented in a moresophisticated read-out chip consisting of charge preamplifier, shaper and analogue memorycell.6. REFERENCES• Philip E. Allen, Douglas R. Holberg, “CMOS Analog Circuit Design” (Holt, Rinehart andWinston, Inc., 1987)     Fig. 4. Gain bandwidth of the output buffer.6Fig. 4. Settling time for 1 V step on the input.Fig. 5. Performance of the multiplexer with 1 V step at the input of one channel and 20 MHzread-out clock.7Fig. 6. Offset variation between AMUX channels - 1V input in channel nr 5.

Fast, low power, analogue multiplexer for readout of multichannel electronics

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