The system consists of a data input subsystem, a display subsystem and a spectrometer control subsystem. The data input subsystem consists of a two-dimensional analog-to-digital converter with the analog section remote from the rest of the system. The analog-to-digital converter clock runs at 100 MHz. There can be up to 1024 channels in each dimension for a maximum array size of approx. 1 million words. Arrays of this size may be easily handled by a multiport memory with 6.71 x 10/sup 7/ words of address space. The read/increment/write time for data in this array is 2.5 ..mu..sec per event. The display and neutron spectrometer subsystem are also briefly described

Alberi, J L

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Presented at 1978 Nuclear Science Symposium, 18-20 October 1978, Shoreham-Americana Hotel, Washington, D. C. To be published in IEEE Trans. Nucl. Sci. * A DATA ACQUISITION AND EXPERIMENT CONTROL SYSTEM FOR A LARGE AREA NEUTRON DETECTOR* J. L. Alberi Brookhaven National Laboratory Upton, New York 11973 October 1978 This research was supported by the U.S. Department of Energy : Contract No . EY-76-C-02-0016. BNL 25132 DISCLAIMER This report was prepared as an account of work sponsored by an agency of the United States Government. Neither the United States Government nor any agency Thereof, nor any of their employees, makes any warranty, express or implied, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any information, apparatus, product, or process disclosed, or represents that its use would not infringe privately owned rights. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise does not necessarily constitute or imply its endorsement, recommendation, or favoring by the United States Government or any agency thereof. The views and opinions of authors expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof. DISCLAIMER Portions of this document may be illegible in electronic image products. Images are produced from the best available original document. arrays, a main program and up to 62 program overlays. For the reasons outlined below, the main program and overlays are coded in FORTRAN. The common node can also accept data from the individual experiment control nodes for spooling on a shared peripheral device (e.g., magnetic tape) for subsequent analysis at the Central Scientific Computing Facility at B~~. Functions of the experiment control and data acquisition node,such as spectrometer control,are ac-cessible via FORTRAN level subroutine calls to system level routines within the experiment control node. Thus, the experimenter, who has intimate knowledge of the logical flow and data structure of his experiment, generates an experiment procedure by using these sub-routines in a FORTRAN program. No other language is· necessary since all special experiment functions are provided in these subroutine calls. The use of the experiment control nodes for any data reduction except that required for validation of data quality is dis-couraged since the typical node lacks the computational power necessary. to reduce data from a complex experiment. Generation of FORTRAN experiment control code takes place on the program development node, which is also part of the network. Code production is made as automated as possible through the use of batch streams on the program development node. Editing, compiling, linking and source library management all are done on this node. The data-acquisition and experiment-control system for the small-angle neutron scattering facility is one of the complex nodes within the network. It has a data rate capacity, data array size and functional complexity beyond that required for most of the other nodes in the network. Yet, due to the generality of the network approach, the experiment is not hindered by the archi-tecture of the system. MEMORY The data acquisition and experiment control node for the small-angle neutron scattering facility may be divided logically into a set of modular subsystems, each with its complement of hardware and software. (As noted previously, all experiment control operations within a particular subsystem are executed by an ap-propriate series of FORTRAN subroutine calls.) The modularity is implemented by the library management and automated linking routines within the program development node. Thus it becomes possible to trans-fer conveniently subsystems from one experiment to another. This technique allows complex systems to be assembled in a relatively short time. Implementation The data-acquisition and experiment-control node for the small-angle neutron scattering facility con-tains two digital processors, one general and one special purpose. The general purpose processor which executes all the experiment control code as described above, is a DEC PDPll/34* with 24 kwords of core memory and a console device. The hardware portions of most of the various subsystems are connected to this processor via the UNIBUS. These include a nine track magnetic tape drive and controller, a storage display terminal for graphical display of data, the neutron spectrometer control electronics package, a paper tape reader, and either a communications link to the common node of the Reactor Experiment Control Facility or a disk. Either one of these devices may be selected. This arrangement is shown in Fig. 1. * DEC and PDP and UNIBUS are registered trademarks of the Digital Equipment Corporation. SCANNER & ~ c UNIBUS ~ = MULTIPORT MEMORY INTERNAL BUS PAPER TAPE I = ADC X,Y READER ADDRESS INFORMATION I = MULTIPORT MEMORY BUS MAGNETIC TAPE CONTROL ADC AND STATUS X CLOCK GATE AN BUSY SIGNALS ANALOC PART OF XADC READ/ 128 kWORDS INCREMENT MEMORY WRITE PROCESSOR FIFO BUFFER ADDRESS SCALERS Y CLOCK GATE AND BUSY SIGNALS ANALOG PART OF Y ADC Fig. 1 Block diagram of data acquisition and experi-ment control node. There are two additional devices connected to the processor UNIBUS, the first of which is the multiport memory. This is a device whereby several processors may communicate to common data arrays contained in a 30 bit address space distinct from the local processor address space (Dimmler and Hardy, .1977). Each proces-sor reads or writes in the memory through an access port. Access to the multiport memory is through a 4096 word window between addresses 140000a and 160000a in the PDPll/34 address space. A 16 bit map register in the processor I/O page provides the high order physical address bits necessary to read or write to a location in the multiport memory. A scanner sequentially interrogates each access port in the node for a read or write request in multiport memory. If a request is pending, the scanner halts for the duration of the re-quest and then continues. Thus each processor in the node has equal priority for reading or writing in the multiport memory. The access port for the PDPll/34 shown at the top of Fig. 1 is connected to both the UNIB~S and the multiport memory internal bus. The second of these two· devices is the dual-parameter analog-to-digital converter. The control and status register, and base address register are connected to the PDPll/34 UNIBUS. The read/increment/ write processor contained in the analog-to-digital converter forms the special purpose second processor of this two processor experiment control node. The general configuration of the analog-to-digital converter is shown in Fig. 1. Data from the two dimensional position-sensitive neutron detector ac-cumulates in the multiport memory where the PDPll/34 can access it through its memory port. Although the PDPll/34 controls the starting and stopping of data collection, and the section of memory into which the data is collected, it does not process individual events in any way. Therefore no interrupts, direct memory transfers, etc., are necessary in the PDPll/34 to collect data. The detailed configuration of the .dual parameter analog-to-digital converter is shown in Fig. 2. Analog data from the x- and y-coordinate position readouts along with start signals arrive at the analog portions of the x- andy-digitizers. These units, which are housed in standard NIM modules, may be remote from the remainder of the experiment control system. They are generally kept close to the position-sensitive detector readout to avoid transmitting sensitive analog signals over long cables. The outputs of these units, the x-and y·-clock gates and busy logic signals, are trans-mitted to 100 MHz address scalers over controlled impedance, shielded, twinaxial cables with good noise immunity. The address scalers have a capacity of 12 bits in each coordinate with address overflow latchup and are implemented in emitter coupled logic. The digitized x- and y-coordinate information then trans-fers to a fast address latch,·which provides one level ADDRESS READY FIFO BUFFER FROM X ANA LOCI DIVIDER X ADC ANALOG PART COLLECT DATA FROM Y ANALOG Y ADC ~;;.._;;=-! ANALOG ,>::.;=~-1 PART X GATE X ADDRESS SCALER FAST ADDRESS LATCH FIFO READY "' COMBINED X,Y ~ ADDRESS TO 24 0 BITS.------. Q < READY~ "' FIFO READY ;1; Y FAST ADDRESS LATCH 0.. ~ f.< "' ~ ADDRESS 24 BITS BASE ADDRESS REGISTER Detailed block diagram of analog-to-digital converter. This is ex-panded from the righthand side of Fig. 1. --, ._:; OUTPUT READY FIRST IN FIRST OUT BUFFER READ/INCREMENT/ WRITE PROCESSOR (SINGLE OR DOOBLE WORD SELECTABLE) UNIBUS of time derandomization. A new event may be digitized after this transfer. The x-and y-addresses are concate-nated in a hardware wireable jumper block. The analog-to-digital converter is currently configured for 7 bits each of x- and y- addresses formed into a 14 bit com-bined address. A 30 bit base address with the top 16 bits settable by tne PDPll/34 is added to the combined x- and y-address to form the physical address to be incremented in multipart memory. This address must fall within the limits selected by the array limit switches otherwise the data is not transferred to multipart memory but ignored. Incoming data is dis-played on binary LED's as a visible indication of proper operation. If the data falls outside the array limits, the LED's latch the erroneous data and an error is indicated. After passing this test a 64 level first-in-first-out buffer accepts the 30 bit physical address. Data from the output of this buffer is then presented to the address lines of the multipart-memory access port, and the read/increment/processor starts its memory cycle. The read/increment/write processor in-crements either a single (16 bit) or double (32 bit) memory location selected by wireable jumper on the circuit module. The node is currently config~red for sin~le word operatiOn since data rates in small-angle neutron scattering are such that overflow is unlikely in a memory cell. If an overflow occurs, the content of the cell is set to all ones to indicate this con-dition. The memory cycle time of the read/increment/ write processor is- 2.5 ~sec including the multipart memory overhead. A timing diagram for an event is shown in Fig. 3 up to the point where data enters the first-in-first-out buffer. TIME IN 1/SEC Q,O .,__ EVEl'.'T TIME, NEUTRON INTERAct'S IN DETECTOR GAS l. 0 4-- DETECTOR RESOLVING TI.ME 2.0 3.0 4-- X ANDy ADC StART PULSE ASSER'l'ED, X ANDY A.DC BUSY ASSERTED .......,__ PEAK DETECTED IN ANALOG INPUT, Cl.OCK CATES ASSER'n:D, ANALOC REA!JCJUT READY FOR NEW EVENT 4.0 5.0 6.0 ...,...__ MAXIMUM CONVERSION nHE , CLOCK GATES NECA TED, BUSY NEGATED 4---- ADDRESSES TRANSFERRED TO FAST ADDRESS LATCH, READY TO ACCEPT NEW DAtA INTO ADC'S .,..._ CC!iBINED ADDRESS TRANSFERRED INTO FIFO BUFFER .,__. FIFO READY FOR NEW ADDRESS -~ Analog-to-digital conversion timing chart for a neutron interaction. The event takes place in the 3He of the detector gas at t = 0.0 ~sec. At t = 1.0 ~ec, the detector elec-tronics is no longer sensitive to event pileup. Two microseconds later, x and y analog position signals are ready for digitization. A new event may start to be digitized at t = 4.7 ~sec, and the first-in-first-out buffer is ready for a new address at t = 5.3 ~sec. The limiting time in the front part of the analog to digital converter is the 3 ~sec taken for analog pro-cessing of the event since the digital portion of the system is ready for a new event- 2.5 ~sec after the start of digitization. Dead time is an important consideration in any such analog-to-digital converter, and, in particular, variations in converter dead time can lead to signifi-cant loss of data accuracy. The multipart memory with its attendent lack of priority structure can cause variation in access port deadtime when the PDPll/34 is transferring data at high rates. The way in which a graphic display of neutron-detector data works demonstrates how this variation in access port dead-time can occur. The PDPll/34 periodically reads the incoming data buffer in multipart memory and displays the data on the graphics terminal attached to its UNIBUS. In the worst possible case, where data is transferred from multipart memory to a buffer in internal PDPll/34 memory, the traLIBfer loop consists of a dual-address autoincrement move instruction, an address compare instruction and a conditional branch instruction, The & inglc pass tilue through this loop is - 9 ~sec for this processor and the multipart memory read time is - 1 ~sec with overhead time added. Thus the analog-to-digital converter access port would be dead 11% of the time during this transfer, thereby increasing the average read/increment/write processor deadtime and causing a variation in data deadtime loss. A simplistic solution to this problem wou~d be to forbid access to the multipart memory by other processors during data collection. This, however, would defeat the purpose of this device. The proper solution is to insert a first-in-first-out buffer for the digitized position data ahead of the analog-to-digital-converter read/increment/write processor. This device converts time-random data at its input to nearly time~pariodic cinta at the output. Thus only the periodic data rate capacity of the read/ increment/write processor is reduced by 117,. If the. time-averaged data rate from the position-sensitive. detector is less than the synchronous data rate capacity of the read/increment/write processor (in the limit of an infinitely deep first-in-first-out buffer), then no data is lost due to read/increment/write processor deadtime. The first-in-first-out buffer used in this node is 64 levels deep so that this relationship is valid. The maximum usable time-averaged data rate from the position-sensitive detector is - 105 events/sec. Thus the read/increment/write processor must update the data in less than - 9 ~sec including multipart memory overhead time if memory accesses from the PDPll/34 are to have negligible effect. This time was demonstrated above to he 2.5 ~sec.· Hence the limiting deadtime in the system is the analog event processing time. Subsystems Each device described above requires control code to develop it into one of the set o·f modular subsystems described previously. Only when these are taken together are the subsystem functions accessible to the user through FORTRAN subroutine calls. Table 1 sum-marizes the subsystem names and functions. Each tabula~ function corresponds to a FORTRAN subroutine call ex-cept where noted. An array in multipart memory is always allocated by a subroutine in the extended FORTRAN array subsystem before use by any other subsystem. The PDPll/34 is understood to be a device used by all sub-systems to execute the appropriate code. Remarks At the beginning of this paper a set of objectives was laid out, some of them rather subjective, for an Table l. Major Subsystems Within the Data Acquisition and Experiment Control Node for the Small-angle Neutron Scattering Facilitv. SUBSYSTEM NAME MAJOR FUNCTION HARDWARE USED BY SUBSYSTEM Analog-to-digital Conversion 1. 2. Set or read base address register 1. Analog-to-digital converter Start data collection to an array in multi- 2. Multiport memory port memory 3. Stop data collection 4. Test for data collection running 5. Collect for pr~set time 6. Collect for preset number of incident beam neutrons. Extended FORTRAN Data Arrays 1. Allocate a FORTRAN array in multiport memory 1. in up to 3 dimensions 2. Test if an array exists 3. Read FORTRAN integer, real, double integer or byte data from an arrayt 4. Write FORTRAN integer, real, double integer or byce daca co an array1' 5. Move data from one array to another. Magnetic !ape 1. Read data in fixed format from 9 track magnetic L Spectrometer Control Graphic Display Overlay tseveral FORTRAN subroutines. tape to an array in multiport memory by specifying file name. 2. Write data to 9 track magnetic tape from an 2. array in multiport memory and name resulting file. 3. List files present on tape. 4. Find a file present·on tape. 1. 2. 3. 4. 5. 6. 1. 1. Set a particular axis in the spectrometer to 1. the specified angle (up to 8 axes). Halt an axis in process of moving Set an angle encoder. Read an axis • Set an axis to zero angle position Position an axis manually to desired angle Consists of a package of commercially available 1. subroutines for graphical display of data on the particular model of display terminal used.t Load a FORTRAN overlay segment from the 1. specified device to the overlay region of PDPll/34 2. Return to main program from current overlay segment. Acknowledgements Multiport memory Nine track magnetic tape unit and controller Multiport memory Neutron spectrometer and controller Storage tube graphics display terminal and interface. Overlay storage device experiment control facility for small angle neutron scattering. The following list summarizes some objective performance specifications for the system. Systems development is always a group enterprise. a). 30 bit address space available for position-sensitive detector data; b) the ability ·to map incoming· detector data into a series of arrays to facilitate time sequential studies ;1 c) simultaneous graphical display and acquisition of data;· d) data losses limited by 3 ~sec detector analog position readout; and e) either 16 bit or 32 bit data at each position location in the two dimensional array. Analysis of the more subjective goals is left to the reader. The author would like to acknowledge the contributions of all members of the BNL systems group including G. Dimmler, N. ·Greenlaw, W. HaJ:dy, M. Kelley, S. Rankowitz and F. Stubblefield. C. WiUiams aided in the prepara-t.ion of this manuscript. References J. Alberi, J. Fischer, V. Radeka, L. Rogers and B. Schoenborn, IEEE Trans. Nucl. Sci., NS-22, No. 1, 255 (1975). J. Cain, J. Norvell and B. Schoenborn, Neutron Scattering for the Analysis of Biological Structures, BNL 50453 (1976). C. Cork, D. Fehr, R. Himlin, W. Vernon, Ng. Xoung and V. Perez-Mendez, Proceedings of the International Conference on Computers in Chemical Research and Educa-tion, Ljubljana-Zagreb, Yugoslavia (1973). D. G. Dimmler, N. Greenla1v, N. Kelley, D. Potter, S. Rank~•itz, and F. Stubblefield, IEEE Trans. Nucl. Sci., NS-23, No. 1, 398 (1976). D. G. Dimmler and W. Hardy, IEEE Trans. Nucl. Sci., NS-24, No. l 469 (1977). R. Hendricks, J. Appl. Cryst. ll• 15 (1978). K. !bel, J. Appl. Cryst. i• 296 (1976). 

Data acquisition and experiment control system for a large area neutron detector

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Data acquisition and experiment control system for a large area neutron detector

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