Work was begun in 1990 on the development of an advanced readout chip (ARC) for silicon strip detectors. Features of the proposed device include compatibility with close bunch spacing and double sided detectors, and on chip analog storage, digitization, and data sparsification. Chip have been designed to check all of these concepts, fabricated in the VTI 2 micron process, and tested. The circuit configurations and test results are presented in this paper

Sarraj, M.

Yarema, R.

Zimmerman, T.

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Fermi National Accelerator Laboratory FERM&iB-Conf-92'316 Design of an Advanced Readout Chip for Silicon Strip Detectors T. Zimmerman, M. Sarraj and R. Yarema Fermi National Accelerator Laboratory P.O. Box 500, Batavia, Illinois 60510 November 1992 Presented at the 1992 IEEE Nuclear Science Symposium, Orlando, Florida, October 26-30, 1992 a Operated by Universities kssarth Association Inc. under Contract No. DE-ACW-76CH03000 witi tfw United States DepaWwmt of Energy DmAaimer This report was prepared as an account of work sponsored by an agency of the United States Government. Neither the United States Government nor any agency thereof, nor any of their employees, makes any warranty, express or implied, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any information, apparatus, product, or process disclosed, or represents that its use would not infringe privately owned rights. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise, does not necessarily constitute or imply its endorsement, recommendation, or favoring by the United States Gouernment or any agency thereof. The views and opinions of authors expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof Design of an Advanced Readout Chip for Silicon Strip Detectors T. Zimmerman, M. Sarraj, R. Yarema Fermi National Accelerator Laboratory* PO. Box 500, Batavia, IL 60510 Abstract Work was begun in 1990 on the development of an advanced readout chip (ARC) for silicon strip detectors. Features of the proposed device include compatibility with close bunch spacing and double sided detectors, and on chip analog storage, digitization, and data sparsification. Chips have been designed to check all of these concepts, fabricated in the VT1 2 micron process, and tested. The circuit configurations and test results are presented in this paper. I. INTRODUCTION +it$%$!Jg~Q P ~ Compaiaior )S RON R CommlllO; n.-.t ‘r , ,p,p,,, ) Lcr ~ Rs‘*r~m~ The requirements of future experiments at Femiilab have created a need for a silicon strip readout chip which can acquire signals at beam interaction times of as fast as 132 ns. A time delay is required to form a trigger, necessitating the use of an analog pipeline to store the signals temporarily. In order to minimize signal processing downstream and maximize readout speed, it is highly desirable to do A/D conversion on the chip. A switched capacitor front end and A/D has been designed at Fermilab which accomplishes these goals. II. CIRCUIT DESIGN AND OPERATION The following important design criteria were adopted for development of the ARC 1). Signal acquisition is stopped during digitization and readout, to reduce input coupling problems, 2). The front end is completely reset every beam crossing to i avoid potential pileup problems which can occur with RC or continuous reset schemes. 3). The risetime is digitally adjustable to accommodate different interaction times, as well as to compensate for the effects of variable input capacitance and process variations on the risetime. 4). A common digitally set threshold is used for data sparsitication of all channels, requiring close attention to compensation of offsets and charge injection. 5). Gain is incorporated into the analog storage stage to eliminate the need for an intermediate gain stage, simplifying device operation. 6). For simplicity and low power dissipation, each channel *Operated by the Universities Research Association under a contrast from the U. S. Department of Energy. Fig. 1 Front end configuration for one channel uses a Wilkinson type A/D with a common counter and ramp. Figure 1 is a block diagram of the resultant design, from the integrator through the comparator (which is part of the Wilkinson A/D). A. Integrator Since the input integrator is loaded with detector capacitance, it is difficult to reset quickly. This leads to a design which has an integrator with a “slow” switched reset and limited gain (and thus large dynamic range), capacitively coupled to a fast amplifier. The bandwidth of the system is limited in the integrator, so that the per bucket fast reset can be accomplished in the amplifier, which is the gain/storage stage in Figure 1. The amplifier then effectively performs a double correlated sample on the integrator output. The integrator most be periodically reset to avoid eventual saturation, and this can be accomplished by performing a slow reset during beam gap intervals and during readout. The integrator is essentially a double cascade configuration with a large PMOS input transistor operating near weak inversion. Since a relatively large current (200 ua) must be set through the input transistor to acheive low noise, the integrator power dissipation represents a substantial portion of the total. Therefore, a reduced power supply (2.7V) is used here to minimize dissipation. Running the input transistor source at a reduced voltage has the added benefit of back biasing the bulk to soorce junction, which reduces the noise contribution of the back gate tramconductance and the bulk resistance (a noise improvement of approximately 15% was measured). The DC reset voltage of the integrator output is adjustable, so the dynamic range can be optimized for either polarity input signal. The risetime of the integrator can be adjusted by switching one or more different valued capacitors onto the dominant node. B. Inverting Stage In order to maximize the available range and simplifiy and optumze the design of the stages following the integrator, a unipolar design philosophy is followed. That is, a negative gong Integrator output is assumed. In order to accept either polarity input signal, an inverting stage (gain=-1) which can be placed in series with the integrator output is required. This is a very simple inverting amplifier with the gain set by feedback capacitor ratio. Inserting the inverting stage in the circuit path results in minimal delay increase and risetime degradation. C. GainlStorage The functions of gain and analog storage can actually be combined into one stage where the feedback capacitor that sets the gain also functions as the storage element (assuming acqulsitum and readout are not desired simultaneously). The smgle stage configuration has several advantages over an approach with separate gain and storage stages: I) a single stage 1s simpler and takes less area and power, 2) fewer switches are required, and 3) the same switches are used for both acquisition and readout. resulting in good charge injection cancellation. The main disadvantage of this approach is that storage capacitor mismatches result in cell to cell gain variations. However, this is acceptable. if the capacitor matching error is less than the A/D resolution. This stage is implemented as a simple double cascade amplifier, which is necessary to obtain sutlicient open loop gam to mamtam accuracy. The fast reset required in this stage can be most easily and effectively implemented by a simple FBT switch between input and output nodes. However, this results in the amplifier output being reset to one end of its range. This is not a problem given that a unipoiar design approach is followed. Opening the reset switch causes charge mJection into the input of the ampiifier. In order to preserve the maxunwn possible time for signal integration, the reset switch charge injection is simply allowed to add to the incoming signal (which is timed to occur immediately after reset release). The resultant sum is then stored. The chae iniection can then be easily subtracted out later during r&out. slew for some. distance before tripping the comparator. However, the configuration shown in Figure 1 requires no external reference. An internal reset reference simpiy sets the DC reset point of the comparator inputs to one end of the range (since operation is unipolar). and there is no offset between the ramp starting point and zero signal. Thus for proper operation, some small signal input is necessary to ensure that the comparator starts out m the proper state. This required signal is typically less than any sparsitication threshold that would be set, so this is deemed acceptabie. zJ.n alternative would be to sunply inject a small offset voltage on the ramp before starting, ens-g digitization of the signal all the way down to zero. E. Ramp Generator and AID Converter The ramp voltage generator driving the AD comparator is implemented as one circuit which is capable of driving all channels in parallel. This eliminates any channel to channel offset which would be caused by individual ramp generators. The design of this block is simplified by the fact that only one polarity ramp is needed The feedback capacitor which sets the ramp rate is made to be of the same type as the integrator feedback capacitor. This provides a very desirable first or&r msensltlwty to system gain variations due to chip to chip Integrator capacitor value variations. A block diagram of the multi-channel A/D scheme is shown in Figure 2. An external clock is gated to an eight bit Gray code counter when the ramp is started. Each channel has a latch which stonx the state of the counter when the comparator IS tripped. To set a threshold. a negative number is loaded into the counter (MSB=I ). Any channel which latches a positive count (MSB=O) is then over threshold and should be read out. Since the MSB is used as a flag, the A/D has effectively seven bits of resolution. The MSB flags from all channels feed a channel prioritizer. which controls the seqwntlal digital readout of the data and address of all channels over threshold. D. Comparator When a pipeline readout and digitization is &G-A 9 ..-“.....,, y  ,,, ,. .:a L.. storage capacitor voltage is compared to a ramp v( Atage by a tugh gam comparator block. The time that is required for the comparator to tnp IS then proportional to the storage capacitor voltage. This design features an AC coupled comparator so that offsets may be nulled. It is typical to provide some sort of external reference which effectively sets the ramp starting voltage and assures that even for zero signal, the ramp must Fig. 2 A/D and re40ut configuration RA - 4 4 4 ~...../ ---- RC e......rj [ ; R s, ___r_i_ & R,, d...... i ~ ~ %UMMI ______~~~... : : RCOUT / ;;I % 1 : -7, RR ------I..~. cz2F’ b...~ Digitizing .~~...e clock LOW = switch open rllGH = Switch closed Fig. 3 Timing diagram F. Clocking scheme Figure 3 is a timing diagram of the proposed clocking scheme. Note that only the gain/storage reset (RC) is operated every interaction. Sampling the signal on a storage capacitor occurs just before the next reset (RSl, RSZ, . ..). The acquisition control signals can be derived from a single master clock. To initiate pipeline readout, an extra dummy storage capacitor is needed to reproduce the charge injection effect of opening the storage reset switch. The comparator reset (RD) is released with this charge injection effect present at the storage output, which will effectively cause it to be subtracted out when reading any other storage capacitor voltage. The dummy capacitor is then removed, and the capacitor of interest is placed in the storage feedback to read out the desired signal voltage. After the A/D counter is reset, the ramp and clock are started. This clocking pattern theoretically subtracts out all offsets and charge injectioneffects. In. -I-EST RESULTS To date, numerous test chips of all sections have been designed and produced using the VTI 2 micron process. Two front end test chips were produced which essentially contain the circuitry up through the storage stage. (Only two storage capautors were used here for simplicity). The first chip actually contains a fast resetable amplifier between the integrator and storage to raise the gain, and the second chip contains only integrator and storage, as in Figure 1. Figure 4 is a hardcopy of the measured risetime of the system (measured at the storage output of the first chip) for two different values of input capacitance. For each case, the risetime has been digitally programmed to three different values that would be approximately appropriate for interaction times of 132 11s~ 200 ns, and 400 ns. This shows that risetime is easily optimized for a variety of conditions. The noise was measured to be approximately 600 electrons + SO e/pf for the 200 ns case, and 700 + SO e/pf for the 132 11s case. Measurements on the second test chip show the speed to be shghtly slower than on the first chip, and the noise to be I” I#“,‘,,” m -“:.. IL.*,,” Cin=1Opf tin= 30 pr Fig. 4 Measured system risetims somewhat higher at approximately 600 electrons + 60 e/pf (200 ns case). The p-formance difference in the two chips is not due to any configuration difference, and seems to indicate run to run differences in performance of the same integrator. The power dissipation of the integrator and gain/storage is about 1 .O mw. An A/D test chip was designed which consisted of eight identical channels, spaced with a 45 micron pitch. Each channnel consisted of a four element storage stage (three active elements plus a dummy) followed by an A/D. Sparsification and readout circuitry served all channels. Testing was performed by injecting different signal amplitudes into one channel at a time, or combinations of channels. Setting a threshold by preloading the Gray counter with a negative number gave the desired result of reading out only those channels above the threshold. When running the digitizing clock at 40 MHz (and toggling the Gray counter on both edges of the clock). digitization of a full scale signal is completed in 1.61~ The test results show that the scheme employed is indeed effective in reducing offsets. The effective offset variation was measured to be 1 mv rms. This includes element to element storage offset in addition to channel to channel comparator offset variations. Gain mismatch, due to capacitor ratio errors, was found to be less than 1%. Since pdy-metall-metal2 capactors were used, this is as expected. The linearity error of the A/D over the full range was less than 0.5%. The quiescent power dissipation of the comparator (relevant for acquisition mode) is about 0.3 mw. IV. CONCLUSIONS A multi-channel silicon strip readout chip has been designed with a fast, programmable risetime integrator, an analog pipeline, and AiD conversion with sparsification. Test chips have been produced which verify all of these concepts. Measurements are very encouraging and show that performance is close to desired Conversion to a 1.2 micron process and complete integration is planned for the near future. 

Design of an advanced readout chip for silicon strip detectors

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Design of an advanced readout chip for silicon strip detectors

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