Current maximum data rates from the Spin Spectrometer of approx. 5000 events/s (up to 1.3 MBytes/s) and minimum analysis requiring at least 3000 operations/event require a CPU cycle time near 70 ns. In order to achieve an effective cycle time of 70 ns, a parallel processing device is proposed where up to 4 independent processors will be implemented in parallel. The individual processors are designed around the Am2910 Microsequencer, the AM29116 ..mu..P, and the Am29517 Multiplier. Satellite histogramming in a mass memory system will be managed by a commercial 16-bit ..mu..P system

Hensley, D.C.

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,,, Presented at 1983 Conf. on Real-Time Computer Applications in Particle and Nuclear Physics,>v Berkeley, Calif., May 16-19, 1983MASTERPARALLEL PROCESSOR FOR FAST EVENT ANALYSISD. C. HensleyOak Ridge National Laboratory*, Oak Ridge, Tennessee 37830SummaryCurrent maximum data rates from the SpinSpectrometer of ~5000 events/s (up to 1.3 MBytes/s)and minimum analysis requiring at least 3000operations/event require a CPU cycle time near 70 ns.In order to achieve an effective cycle time of 70 ns,a parallel processing device is proposed where up to4 independent processors will be implemented inparallel. The individual processors are designedaround the Am2910 Microsequencer, the AM2S116 yP, andthe Am29517 Multiplier, Satellite histogramming in amass memory system will be managed by a commercial16-bit uP system.IntroductionThe Spin Spectrometer* at the Hoiifield HeavyIon Research Facility is a 4* y-ray detector systemconsisting of up to 72 Nal detectors of aqua? solidangle. Heavy ion reactions of current interest pro-duce more than 20 y rays on the average and from 2 to12 neutrons. Consequently, the average number ofdetectors involved in a single event may be 30 ormore, and the numbe." of bytes per event readilyaverages 250 or more. The Event Handler driven CAMACbased data acquisition system2 is currently limitedby ADC conversion time and data read-out time toevent rates of about 5000 events/s.The present possible data acquisition rateexceeds our ability either to transmit data to thecomputer or to spool it thence onto tape. Thus, anypreprocessing which might reduce the data trans-mission rate without reducing the event rate ishighly desirable.CONF-830576—4DE83 014050Further, various levels of processing of the data arerequired before detailed analysis can be done, andways of speeding up these processing phases areclearly needed. To perform the standard first passprocessing, approximately 3000 CPU operations peraverage event are needed as a minimum, and moredetailed processing would definitely be desired. Arate of 5000 events/s with 3000 operations/eventimplies an operation time of -66 ns. Although manyapplications of such a processor will be for signifi-cantly lower data rates, a CPU cycle time less than70 ns seems a desirable goal, since the analysismight be correspondingly more complicated.An effective CPU cycle time less than 70 ns canmost easily be achieved for this application with theuse of parallel processors since the data stream hasnatural divisions at event boundaries. Theprocessing of a particular event can be handledessentially independently of that for another event.If it is assumed that the necessary analysis programsare both relatively simple (no floating pointcalculations) and relatively small {<4k instructions),a CPU cycle time near 200 ns is reasonable, and a setof 4 parallel processors would achieve an effectivecycle time near 70 ns.Overview of the SystemThe parallel processing system wi l l consistof the following modules (see Fig. 1): A commercial•Operated by Union Carbide Corporation under contractW-7405-eng-26 with the U.S. Department of Energy.CAMAC//////1 NC1•1)CC HOSTnoWNi "AnTAPES'PARALLELPROCESSORS-i/ j MEMORY N4 DATAACQUISITIONSYSTEMrrff; k 'Ani01JTMASSMEMORYHOSTTAPESCAMACF I G .DISTRIBUTION OF THIS DOCUMENT IS UNLIMITED• V «CC»T*nc* ©» TMt trticl*. ihtubUttw cr rM!0*nt*cfcne*ri»4th« U.S. Gewernt***!'* rtfftt torttsin * n£r«*»ciutiv*. rsyattv frtleinii in »nij TO »ny cDttv>3*tcrate controller(s) for interfacing to the hostcomputer(s). There wvl 1 be an INPUT module and anFIFO-OUTPUT module in CAMAC. In addition to theparallel processors (PP), there wil l be a sharedMEMORY module, and a random-time access OUTPUT moduleInterfacing to a mass memory and MPs system.The crate controller permits the host computerto download programs into the processors and to placeconstants/data into the processors and the memory.When the processor system is running, the host com-puter uses the INPUT/OUTPUT modules to effect blocktransfers of data with the processors.The INPUT module has two distinct functions,downloading the processors and memory and d i s t r i -buting entire events to different processors. Theevent stream is extracted from an incoming FIFOdata stream.Downloading the processors requires that theINPUT module be able to select one or more proces-sors, disable i t , and transfer both addresses andprogram code—memory verification would be doneusing the same interface. In the usual case whereeach processor uses the same program, all processorscould be downloaded in parallel. The INPUT modulehas no direct connection to the data storage of theprocessors, so i t must use a processor program totransfer data through an input register to thesememori es.Data for processing is input through a FIFOmemory of at least 4k words. Input to this memorycan be from the host computer via the CAMAC datawayor from the data acquisition system (DAS) through afront panel input. The INPUT module handles theprocessor selection and the transferring of anentire event to an available processor. Data trans-fers can be up to 24 aits wide, but the processorswil l typically analyze only IS of the bits.The OUTPUT module also contains a FIFO buffermemory of at least 4k words. The OUTPUT modulecontrols \>hich of the processors i t wil l service,but i t generally takes an entire event of data froma processor before i t tries to service anotherprocessor. The module services the processors in amixed mode of first-come-first-served and round-robin— this mode ensures that no processor can belocked out by the other processors. Note that theorder of events out need no longer be the same asthat in , but i t should be reasonably close. The FIFOmemory can be accessed via the CAMAC dataway or via afront panel FIFO output port.The memory module is to contain 64k words (16bits) of fast memory which can be accessed via a r ib-bon cable connected to the processors. Access on arequest/grant basis wi l l give the processors a largememory capability. The memory can be used to storememory-mapped-gates, free-form-gates, or other commoninformation too extensive to be stored in the indi-vidual processor memories. I t can also contain com-mon information which is being changed during thecourse of the processing, such as a softwarestabilized gain. I t can also serve as a histogrammingmemory for the processors.The processor section of the parallel processorswil l be described below. The CAMAC link to the proc-essors through the INPUT module allows the programand data memory to be written/verified by the hostcomputer. The processor can be disabled/enabledthrough the INPUT module. The processor is able togenerate both an "available" LAM and an "outputready" LAM, and FIFO block transfers of events isaccomplished under processor program control throughthe INPUT and OUTPUT modules. No special provisionhas been made to allow processors to have differentprograms, but i f one processor is programmed to beindependent of the input event stream, i t can runindependently.Details of the ProcessorsThe processors in the parallel processor systemwi l l be optimized for 16 b i t I/O and data. Eventhough CAMAC possesses a 24 bi t capability, in prac-tice at Holi f ield Heavy Ion Research Facil i ty only 16bi t data acquisition is performed, and a 16 b i t l im i -tation seems quite acceptable.The program memory wi l l be limited to 4k ofmicrocode (96 bits maximum). Most programs shoulduse far fewer operation locations than this for theirexecution, particularly since I/O wi l l be limited toquasi-DMA interchanges with the INPUT and OUTPUTmodules. The program memory wi l l not be alterable bythe program.The work memory wil l consist of from 4k words(16 bits) to 12k words. Part of this space wi l l beworking space and part wi l l consist of predeterminedconstants and data. The predetermined constantswould include energy calibrations, ADC pedestals,etc., and other fixed constants such as reciprocalsfor performing fast divisions.The processor wi l l be bui l t around three dif-ferent devices, the Am2910 Microprogram Controller,the Am29116 16-bit Bipolar Microprocessor, and theAm29517 16 by 16 bi t Parallel Mult ipl ier as shown inFig. 2. All of these devices feature cycle tinecapabilities of at least 100 ns, so that with 50 nsaccess-time memory an overall cycle time near 200 nsseems feasible. These devices wi l l be driven inparallel by horizontal microcode as shown in Fig. 2.In principle the Am29116 and Am29517 could be workingin paral lel, but much code wi l l not be able to \izethis feature because these devices share the 16-t>itI/O bus. On the other hand, the Am29iC and the spe-cial registers wi l l be running largely independently,and some paralle1 processing capability with themwi l l be possible.The Am2910 features a 12-bit address output, 4address sources, a 5 deep subroutine stack, a con-ditional test input, an internal loop counter, and 16microinstructions. Basically i t allows absolutejumps, conditional jumps, and fu l l subroutine capa-b i l i t y , and i t requires up to 11 controls in additionto a 12 b i t address input and 12 b i t output.The Am29116 is a 16 b i t , 100 ns cycle timeprocessor with arithmetic logic and an accumulator,up to 15 bi t rotations or shi f ts , b i t orientedoperations (set, mask, and clear), pr ior i ty encoding,32 internal registers storage, an input latch, andextensive condition code generation. I t requires upto 26 control inputs in addition to i ts 16 I/O l ines.I t can use as i ts data sources various combinationsof the Internal registers, the accumulator, the inputlatch, the external inputs, or even the controlinputs. I ts result can be routed to the internalregisters, the accumulator, the input latch, or tothe output l ines. The status word can be read or asimple test condition can be requested and sampledwhile the Am29116 is executing an instruction.,12CAMACDatawoyInterfaceAm 2910Sequencer12P MEMORY 4k x 96I6 , 9 6PIPELINE REGISTERAm295l7multiplier25 ' 16Am29ll6*16 BIT BUS UM\±26SpecialRegistersADDERClockGeneratorINPUTOUTPUTDATA MEMORY12k x !6PROCESSING UNITFig. 2The Am29517 is a fast (~S0 ns) 16 by 15 b i tmultiplier with the fu l l 32 bit product multiplexedat the output. I t can handle TWO's complement,unsigned, or mixed operands. I t requires up to 12control lines and has three separate 16 lineinput/output ports.In addition to these three devices, there aremany registers which perform various internal andinterface functions. There wil l be address/indexregisters which allow data to be accessed at separa-tely specified locations. These registers can beincremented at the end of a cycle in parallel withany of the main devices, and zero detection wi l l beavailable for conditional testing. A random numberregister wi l l allow smoothing of modified ADC infor-mation, and a shi f t /pr ior i ty register wil l enhancethe u t i l i t y of the Ara29U6. A buffer register forthe multiplier chip may be desirable.Input/output wi l l also be handled throughregisters. There wil l be an input and an outputregister for FIFO-like data transfers, and therewil l be a 32 bi t wide register for output to ahistograircning device. Finally a pair of registerswi l l handle I/O with the memory module.Satell i te u ProcessorI t is proposed that a satel l i te uP system accom-pany the parallel processor system. This would be asystem bui l t around a device comparable to theMC68000 uP and would include a mass memory (at leastseveral KBytes), interfaces to the host computer andto the output module of the parallel processor system.and some very modest display capability. I ts mainuse would be as a fast, large histogramming memory,or i t could be used for f i r s t stage histogramnring forvery large histograms.We typically use histogramming for two differentphases of our experiments. The f i r s t phase is themonitoring of online data acquisition. Histograms ofmost of the parameters wi l l be generated in order tocheck the gain, threshold, resolution, integri ty,etc. , of the parameters. This is done during thesetup of the experiment and during the course of theexperiment. Generally these histograms ^re not usedin the final data reduction. In a few cases wherethe experimental system is reliable and relativelysimple, these histograms nay constitute a l l or mostcf the final data acquisition.For more complicated data acquisition systems,the data are spooled directly onto magnetic tape, andthe tapes are replayed to generate the final reduceddata. In many cases, these replays generate verylarge histograms, but i f the available histogrammingspace is large enough, the replaying of the tapes canbe minimized.In either case, histograrnming in the main com-puter can be unsatisfactory because i t is both memoryand CPU intensive. I f the main computer doeshistogramming during data acquisition, this activitymay l imit the data rate or provide a too small sampleof the data stream. During processing of data tapes,the histogramming function ties up the CPU and memoryfrom other users and may cause th*> tape processing toproceed too slowly.I f the parallel processor system generateshistogram addresses which i t passes on to the satel l i tesystem, the entire histogramming load is removedfrom the main computer which is le f t free for tapeI/O, interactive displaying, and data analysis.In the event that the histogram space exceedsthe size of the mass memory, the system can s t i l l beused effectively as a "prehistogrammer." Random add-one access to a 16 megachannel array on disk canproceed at an average rate near 10 kHz. I f thesatel l i te system had 4 MSytes of memory, i t couldassign 2 bits per channel to the histogramming andreduce the input rate to the main computer by afactor of 4. Then an average updating rate near 40kHz could be achieved.Use of the SystemThere are several intended uses of this parallelprocessing system (PPS). The event source can beeither the data acquisition system (DAS) (1.3MBytes/s maximum) or data tapes read by the maincomputer (0.7 MBytes/s maximum). The output destina-tion can be either tapes on the main computer,histograms in the main computer, or histograms in thesatel l i te uP system. The following are the main con-fi-ju itions to be used:TapesuP HistogramsTapesvP HistogramsTAPESIn a l l o f these c o n f i g u r a t i o n s , the main computer i srequ i red to perform block I/O which i t does veryeff ic ient ly , almost effortlessly, and i t is notrequired to make calculations and decisions which i tdoes powerfully but slowly.'Why This SystemWhile it is reasonably clear that parallel proc-essing is desirable, why design this particular spe-cial processor? The approach of the "MIDAS"3 projectat Berkeley has been to use a modern CPU, stripped ofextras, while SLAC has developed the 168/E," whichemulates a subsat of the IBM 360/370 -instruction set.Both laboratories run their processors in parallel toachieve high computing power, and both systems canhandle complicated calculations. A special strengthof these systems is that they can use sr^twa'e whichruns on the host computer. For a large class ofexperiments in nuclear physics, these approaches seemmore powerful than necessary and hence more expen-sive and complicated. Thus, while they may presentone of the best solutions to many problems, they maynot be the best match to the present problem.The current class of 16 bit microprocessors cer-tainly presents another alternative. They have theadvantage of relatively low cost, powerful instruc-tion sets, and growing software support. On thewhole, however, they seem to be mismatched to thecurrent problem; their effective speed would probablybe at least a factor of four too slow.The proposed processor has certain weaknesses.It and its software have to be designed and debugged.It does not directly have a divide function.Floating point calculational capability has beenignored in its design. However, more than sufficientnumerical precision can be achieved with 16 b:tintegers for all of the proposed calculations.Seldom is there a need to divide, and fast divisioncan and will be achieved through multiplication by areciprocal. The horizontal nature of the microcodeappears to allow useful parallel operation thatfurther enhances the processor's speed. On thewhole, the proposed processor should in fact be espe-cially effective in processing the Spin Spectrometerdata, either online or offline.References1. D. G. Sarantites et a]_., Journal De Physique,Colloque CIO, Sup'pTenent au n° 12, Vol. 41,C10-269 (1980).2. D. C. Hensley, IEEE Trans. Nucl. Sci. NS-28, No.5, 3720 (1981).3. C. Maples, W. Rathbun, D. Weaver and J. Meng,IEEE Trans. Nucl. Sci. NS-28, No. 5, 3745 (1981).4. P. F. Kunz et al., "The LASS Hardware Processor,"Proc. 11th TSmin Microprogramming Workshop,SieilCRO Newsletter 9, 25 (1978).DISCLAIMERThis report was prepared as an account of work sponsored by an agency of theUnited States Government. Neither the United States Government nor any agencythereof, nor any of their employees, makes any warranty, express or implied, orassumes any legal liability or responsibility for the accuracy, completeness, or use-fulness of any information, apparatus, product, or process disclosed, or representsthat its use would not infringe privately owned rights. Reference herein to any spe-cific commercial product, process, or service by trade name, trademark, manufac-turer, or otherwise does not necessarily constitute or imply its endorsement, recom-mendation, or favoring by the United States Government or any agency thereof.The views and opinions of authors expressed herein do not necessarily state orreflect those of the United States Government or any agency thereof.

Parallel processor for fast event analysis

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Parallel processor for fast event analysis

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