Modern computing systems predominantly operate on the binary number system that accepts only ‘0’ or ‘1’ as logical values leading to computational homogeneity. But this helps in creating leakage patterns that can be exploited by adversaries to carry out hardware and software-level attacks. Recent research has shown that ternary systems, operating on three logical values (‘0′, ‘1\u27, and ‘z\u27) can surpass binary systems in terms of performance and security.  In this paper, we first propose a novel approach that assigns logical values based on the direction of current flow within a conducting element, rather than relying on the voltage scale. Furthermore, we also present the mathematical models for each ternary gate

Dipesh

Urbi chatterjee

Vishesh Mishra

Cryptology ePrint Archive

B2T: The Third Logical Value of a BitDipeshDept. of CSEIIT Kanpur, Indiadipesh@cse.iitk.ac.inVishesh MishraDept. of CSEIIT Kanpur, Indiavishesh@cse.iitk.ac.inUrbi ChatterjeeDept. of CSEIIT Kanpur, Indiaurbic@cse.iitk.ac.inAbstract—Modern computing systems predominantly operateon the binary number system that accepts only ‘0’ or ‘1’ aslogical values leading to computational homogeneity. But thishelps in creating leakage patterns that can be exploited byadversaries to carry out hardware and software-level attacks.Recent research has shown that ternary systems, operating onthree logical values (‘0, ‘1’, and ‘z’) can surpass binary systemsin terms of performance and security. In this paper, we firstpropose a novel approach that assigns logical values based onthe direction of current flow within a conducting element, ratherthan relying on the voltage scale. Furthermore, we also presentthe mathematical models for each ternary gate.Index Terms—Ternary System, HDL, Mathematical ModelI. INTRODUCTIONModern computers operate on a binary system that con-sists of only two logical values, namely ‘0’ and ‘1’, whichcorrespond to a true or false state. However, with moore’slaw reaching its limits, it has been difficult to cater to theever-increasing computational demands through conventionalbinary-based computations. In addition, binary system facili-tates a pattern of computational homogeneity that results in athreat to the secret key entropy in the majority of cryptographicimplementations [1], [2].Modern computer applications, particularly machine learn-ing, artificial intelligence, and scientific computing, generatesubstantial data computations that strain binary-based systems.To overcome these challenges, researchers have been exploringalternative computing approaches, including quantum comput-ing, in-memory computing, and approximate computing, tomake computation faster and more secure. Moreover, they haveshown increasing interest in alternative number systems, offer-ing advantages beyond the traditional binary system. Researchalso shows that ternary-based cryptography performs betterthan traditional binary-based cryptography not only in termsof computation and energy [3] but also in terms of security[4], [5]. In response to these opportunities, recent works [6]have emerged, focusing on designing and implementing theternary number system with a radix of three. This ternarysystem shows promising advantages over the binary systemregarding computation and security.Unlike previous studies, we investigate using three ternarylogic values (0, 1, and z) within existing binary logic gates.By incorporating ternary logic into the binary framework,we aim to expand design possibilities and improve logiccircuit functionality. The key contributions of this work areas follows:• We adapt the hardware to implement ternary number sys-tems by utilizing high impedance ‘Z’ in conducting elementsas a third logical value of a bit.• Unlike traditional transistor-level designs, our unique ap-proach integrates ternary logic into existing logic gates. Wevalidated this using Hardware Description Language (HDL)Verilog and formulated the mathematical functionalities oflogical gates within the ternary system.II. PROPOSED TERNARY SYSTEMThe existing binary system works on two logical values:0 and 1. At the hardware level, zero corresponds to theabsence of an electrical signal or a low voltage level (usuallyclose to 0 volts), while one represents the presence of anelectrical signal or a high voltage level (usually at a specifiedvoltage, often referred to as the logic-high level). Alternatively,it can also be attributed to the current movement inside aconducting element. For instance, the current movement fromanode to cathode due to the high potential difference (e.g.,5V) is considered logical ‘1’. If the movement is in thereverse direction ( reverse saturation current) or in the samedirection (but due to significantly low potential difference), itis considered logical ‘0’. Interestingly, there can be a thirdpossibility as well. For example, there is a high impedanceinside the wire, (represented using ‘Z’ in Verilog HDL) orthe flowing current is significantly low (i.e., less than a pre-defined threshold value) which can be used as our third logicalvalue for a bit. This way, the conducting element now hasthree possible values viz., 0,1, and Z depending upon the netmovement of electrons inside it. The same convention canbe used to define the state of storage elements e.g. capacitor,which is defined as follows:• Logical 1; if Q/C >= T .• Logical 0; if Q/C < T .• X as used in HDL like verilog; if Q = 0.Using symbols Q,C, T , we relate to the charge, capacitance,and threshold voltage of a capacitor. Unlike binary systemslimited to 0 and 1, we introduce a third option, Z, for wires,and X for registers. This extends to a new number systemwhere elements can be 0, 1, Z, or X. This introduces a ternarysystem, offering three possible values to depict the state ofeach conductor or storage unit. Figure 1, 2, and 3 brieflyexplain the movement of electrons corresponding to theselogical values.Free  ElectronsConducting Element Electrons FlowConventional Flow+_Fig. 1. Illustration of the movement of electrons inside the conducting element(from cathode to anode). This shows that the current direction is from anodeto cathode, and the negative potential difference between cathode and anode issignificantly high. This is considered a logical 0 in the binary representation.Free  ElectronsConducting Element Electrons FlowConventional Flow+_Fig. 2. Illustration of the movement of electrons inside the conductingelement (from anode to cathode). This shows that the current direction is fromcathode to anode, and the potential difference between cathode and anode issignificantly high. This is considered logical 1 in the binary representation.Free  ElectronsConducting Element+_Fig. 3. Illustration of the movement of electrons inside the conducting elementis entirely random, and as a net result, they cancel out each other. This meansthere is no net movement (or neglectable) of electrons inside the conductingelement. This results in a high impedance denoted as Z in conventionalhardware description language like Verilog.A. Logical gates behaviour with ternary inputsThe binary input behavior in logical gates is well-known,our study pioneers by exploring how these gates work withternary inputs (’Z/X’).To conduct our research, we adopteda hit-and-try methodology, introducing a third logical valuealongside the conventional binary values and meticulouslyobserving the resulting outputs for each logical gate. Our aimis to grasp the influence of ternary inputs on the overall perfor-mance and functionality of these gates during ASIC synthesis.For the simulations, we employed advanced Computer-AidedDesign tools (CAD) like Iverilog V11 to define the behaviourof circuits accurately. Using the Hardware Description Lan-guage (HDL) to assign Z or X values as inputs allows a deepexamination of how existing logical gates behave with ternaryinputs. Our study utilized Verilog to analyze existing logicalgates like AND, OR, NOT, NOR, NAND, XOR, and XNOR.Our research seeks to answer questions such as:1. How does the introduction of ternary inputs impact thetruth tables and logical behavior of each gate? 2. Can ternaryinputs enhance the fault tolerance and reliability of digitalcircuits? 3. Are there any unique applications for ternaryinputs in specialized computing environments? 4. What are thelimitations and challenges associated with integrating ternaryinputs in practical circuits?By undertaking this innovative investigation, we hope topave the way for the adoption of ternary inputs in logicdesign, opening up new possibilities for digital circuitry andpotentially leading to advancements in computing systems andtheir applications.In conclusion, our study aims to shed light on the function-ality and viability of ternary inputs in logical gates, bringingattention to this unexplored area of research and inspiringfurther exploration into the world of ternary logic. The resultsof our experiments will contribute to the broader understandingof logic design and may spark new paradigms in digitalcomputing.TABLE ITRUTH TABLE FOR LOGIC GATES WITH TERNARY INPUTSA B AND OR NOT NAND NOR XOR XNOR0 0 0 0 1 1 1 0 10 1 0 1 1 1 0 1 00 Z 0 X 1 1 X X X0 X 0 X 1 1 X X X1 0 0 1 0 1 0 1 01 1 1 1 0 0 0 0 11 Z Z 1 0 X 0 X X1 X X 1 0 X 0 X XZ 0 0 X X 1 X X XZ 1 Z 1 X X 0 X XZ Z Z X X X X X XZ X X X X X X X XX 0 0 X X 1 X X XX 1 X 1 X X 0 X XX Z X X X X X X XX X X X X X X X XThe results in Table I are crucial, forming a foundation toexamine established logical gates with a new input set: logical0, logical 1, and logical Z/X. While we understand outcomesfor logical 1 and 0, our focus is on unraveling how gatesbehave when one or both inputs are logical Z/X. This helpsus understand gate responses to uncertain inputs representedby logical Z/X. The experimental results are presented in TableI. In this table, columns A and B represent the inputs providedto the aforementioned logical gates. The remaining columnsrepresent the corresponding outputs of these gates, based onthe given inputs in columns A and B. It is important to notethat the output of the NOT gate corresponds to the input ’A,’as it is a single-input gate.More precisely, the findings of the experiment are as follows:• Gates show normal behaviour with the Z/X as an input tothe logical gates.• X is shown in the output even though we have not providedX as a single input.• Z does not appear at a single output, even if both inputs ofa gate have provided Z as an input.• No error is seen in the Verilog simulator.Based on these findings, we draw several conclusions that arelisted as follows:• The existing logical gates are designed to work on a ternarynumber system.• Both the binary and ternary number systems, can run on thesame hardware.• The register cannot hold Z as a value.• Z and X are equivalent on the hardware level as when Z ispassed to a buffer, it is converted to X, but X remains X onthe same experiment.Additional note: X is used to represent both X/Z at the sametime, as they are equivalent in the findings.Our experiments have showcased the behavior of each logicgate. Based on the behavior and its analysis, we now aim torealize each logic gate in a mathematical form with the help ofa function f . Clearly, the domain and range of this functionf is defined over set B = {−1, 0, 1}. Here, each elementrepresents the net movement of electrons inside the conductingelement viz., -1 represents logical 0, 1 represents logical 1, and0 represents high impedance. The function f has the numberof parameters depends upon the type of logical gate, whichis 2 in most gates, except NOT gate, in which the number ofparameters is 1. However, the function always returns a singlevalue.B. Functionality of logical gatesThe functionality of each logical gate is defined using thefunction f . The domain and range of each function is the setB as defined above. The functionality of each logic gate isdefined using the observations and findings of table I.• AND Gate:- The outputs corresponding to each input areshown in Table I. As shown, ’0’ is returned when one inputis ’0’, ’X’ is returned when one or both of input/s is/are ’X’,and another input is not ’0’, and ’1’ is returned when bothinputs are ’1’. From the above observation, we conclude thatthe maximum of the passed parameter values is returned.Consequently, functionality f is defined as:f(A,B) ={B if A >= BA if B > A}(1)• OR Gate:- The outputs corresponding to each input areshown in Table I. As shown, ’1’ is returned when one inputis ’1’, ’X’ is returned when one or both of input/s is/are’X’, and another input is not ’1’, and ’0’ is returned whenboth inputs are ’0’. From the above observation, we definethe functionality f as:f(A,B) ={A if A >= BB if B > A}(2)• NOT Gate:- The outputs corresponding to each input areshown in Table I. As shown, ’1’ is returned when input is’0’, ’X’ is returned when input is ’X’, and ’1’ is returnedwhen input is ’0’. From the above observation, concludethat the additive inverse of the passed parameter value isreturned. Also, functionality f is defined as:f(A) = −A (3)• NAND Gate:- The outputs corresponding to each input areshown in Table I. As shown, ’1’ is returned when one inputis ’0’, ’X’ is returned when one or both of input/s is/are ’X’,and another input is not ’0’, and ’0’ is returned when bothinputs are ’1’. From the above observation, we conclude thatthe additive inverse of the maximum of the passed parametervalues is returned. Consequently, functionality f is definedas:f(A,B) = −Cwhere C ={B if A >= BA if B > A}(4)• NOR Gate:- The outputs corresponding to each input areshown in Table I. As shown, ’0’ is returned when one inputis ’1’, ’X’ is returned when one or both of input/s is/are’X’, and another input is not ’1’, and ’1’ is returned whenboth inputs are ’0’. From the above observation, we areable to conclude that the additive inverse of the minimumof the passed parameter values is returned. Consequently,functionality f is defined as:f(A,B) = −Cwhere C ={A if A >= BB if B > A}(5)• XOR Gate:- The outputs corresponding to each input areshown in Table I. As shown, ’0’ is returned when both inputsare the same and not ’X’, ’X’ is returned when one input is’X’, and ’1’ is returned when both inputs are not the sameand not ’X’. From the above observation, we conclude thatthe additive inverse of the product of the passed parametervalues is returned. Also, functionality f is defined as:f(A,B) = −(A.B) (6)• XNOR Gate:- The outputs corresponding to each input areshown in Table I. As shown, ’1’ is returned when both inputsare the same and not ’X’, ’X’ is returned when one input is’X’, and ’0’ is returned when both inputs are not the sameand not ’X’. From the above observation, we deduce thatthe product of the passed parameter values is returned withfunctionality, f defined as:f(A,B) = (A.B) (7)III. CONCLUSIONThis paper highlights the practicality of employing theternary number system on existing hardware. By analyzing thebehavior of logical gates in the context of a ternary numbersystem, we establish a mathematical model applicable to bothbinary and ternary systems.REFERENCES[1] S. Mangard et al., “Successfully attacking masked aes hardware imple-mentations,” in International Workshop on Cryptographic Hardware andEmbedded Systems. Springer, 2005, pp. 157–171.[2] M. Tunstall, D. Mukhopadhyay, and S. Ali, “Differential fault analysisof the advanced encryption standard using a single fault,” in InformationSecurity Theory and Practice. Security and Privacy of Mobile Devicesin Wireless Communication: 5th IFIP WG 11.2 International Workshop,WISTP 2011, Heraklion, Crete, Greece, June 1-3, 2011. Proceedings 5.Springer, 2011, pp. 224–233.[3] W. Alexander, “The ternary computer,” Electronics and Power, vol. 10,no. 2, pp. 36–39, 1964.[4] R. Bricout et al., “Ternary syndrome decoding with large weight,” in Se-lected Areas in Cryptography–SAC 2019: 26th International Conference,Waterloo, ON, Canada, August 12–16, 2019, Revised Selected Papers 26.Springer, 2020, pp. 437–466.[5] J. Adikari et al., “Hybrid binary-ternary number system for elliptic curvecryptosystems,” IEEE transactions on computers, vol. 60, 2010.[6] S. Lin, Y.-B. Kim, and F. Lombardi, “A novel cntfet-based ternary logicgate design,” in 2009 52nd IEEE International Midwest Symposium onCircuits and Systems. IEEE, 2009, pp. 435–438.

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