Institute of Electrical and Electronics Engineers Inc.
Doi
Abstract
This paper presents an efficient solution to reduce the power consumption of the popular
linear feedback shift register by exploiting the gated clock approach. The power reduction with respect to
other gated clock schemes is obtained by an efficient implementation of the logic gates and properly
reducing the number of XOR gates in the feedback network. Transistor level simulations are performed by
using standard cells in a 28-nm FD-SOI CMOS technology and a 300-MHz clock. Simulation results show
a power reduction with respect to traditional implementations, which reaches values higher than 30%