This dissertation presents an incremental analog-to-digital converter (ADC) with digital digital-to-analog converter (DAC) mismatch correction. A theoretical time-domain analysis technique was developed to predict the noise performance of the incremental ADC, and a new optimization technique was proposed to minimize the output noise.
In the calibration mode, the incremental ADC itself is used to measure the mismatches of the internal multi-bit DAC. Three new calibration techniques, equation-solving calibration, inter-DAC mismatch calibration and modified “Sarhang-Nejad” calibration are proposed.
To verify the above techniques, a test chip was designed and fabricated in 0.18 µm CMOS process. The chip can work in single-sampling or double-sampling mode. Chopping with a fractal sequence is used to eliminate 1/f noise. The calibration circuit was implemented to calibrate the multi-bit DAC mismatches the in single-sampling mode and inter-DAC mismatches in the double-sampling mode.
Finally, two new design techniques for low-power ADCs, the two-step split-junction successive-approximation register (SAR) ADC and the hybrid cascaded ∆Σ ADC, are proposed
