Dynamically scheduled high-level synthesis (HLS) enables the use of
load-store queues (LSQs) which can disambiguate data hazards at circuit
runtime, increasing throughput in codes with unpredictable memory accesses.
However, the increased throughput comes at the price of lower clock frequency
and higher resource usage compared to statically scheduled circuits without
LSQs. The lower frequency often nullifies any throughput improvements over
static scheduling, while the resource usage becomes prohibitively expensive
with large queue sizes. This paper presents a method for achieving dynamically
scheduled memory operations in HLS without significant clock period and
resource usage increase. We present a novel LSQ based on shift-registers
enabled by the opportunity to specialize queue sizes to a target code in HLS.
We show a method to speculatively allocate addresses to our LSQ, significantly
increasing pipeline parallelism in codes that could not benefit from an LSQ
before. In stark contrast to traditional load value speculation, we do not
require pipeline replays and have no overhead on misspeculation. On a set of
benchmarks with data hazards, our approach achieves an average speedup of
11× against static HLS and 5× against dynamic HLS that uses a
state of the art LSQ from previous work. Our LSQ also uses several times fewer
resources, scaling to queues with hundreds of entries, and supports both
on-chip and off-chip memory.Comment: To appear in the International Conference on Field Programmable
Technology (FPT'23), Yokohama, Japan, 11-14 December 202