Integrated injection logic (1,2) technology for reliable operation under a -55 C to +300 C, temperature range is discussed. Experimental measurements indicate that an 80 mv signal swing is available at 300 C with 100 micro A injection current per gate. In addition, modeling results predict how large gate fan-ins can decrease the maximum thermal operational limits. These operational limits and the longterm reliability factors associated with device metallization are evaluated via specialized test mask

Dening, D. C.

Lee, C. Y.

Ragonese, L. J.

English

NASA Technical Reports Server

HIGH TEMPERATURE LS1 
D .C . Dening, L . J . Ragonese, and C .Y . Lee 
General Electric Electronics Laboratory 
Electronics Park - Room #I09 
Syracuse, New York 13221 
Post Office Box 4840 
Summary 
The General Electric Company has been bv+Aved 
in developing Integrated Injection Logic ( I ~ L  ) 
tech ology for reliable operation under a -55% to 
+300VC, temperature range . Experimental measure - 
meats indicate Wit an 80 mv signal swing i s  av'lilable 
a t  300°C with 100 HA injection current per gate. In 
addition, modeirng rt ;d t s  predict how large gat" 
fan -ins can decrease the maximum thermal ?pera - 
tional limits. These operational limits and the long- 
term reliability factors associated with device metal- 
lizations are  bling evaluated via specialized test 
mask. 
The correct functional operation of large scale 
integrated circuits ir. a -55% to +300°c temprature 
environment for long periods of time will provide 
substantial immediate benefits f ~ r  digital jet aircraft 
engine control and geothermal or  deep fossil-fuel 
well logging. Most .?ommerciaLly available LS1 tech- 
nolo@e; are  inoperable or suffer long-term instabil- 
ities u d e r  these conditions. 
introduction 
--- 
There is no inherent reason why silicon bipolar 
devices will not cperate at +300°C for extendeu 
periods of time, provided the circuit has been prop - 
erly designed to tolemte leakage currents in that en- 
vironment. A calculation using extrapolated diffusion 
coefficients for aluminum in silicon (the worst-case 
dopant) at  5 0 0 ~ ~  indicates that p-a junctions would 
not move appreciably in 1990 years. However, other 
contaminants such a s  gnld ; copper not con~monly 
desired in unlimited quantities have difiusion coeffi- 
cients at least ten 0rder.r of magnitude higher. In 
addition, the metal interconllcction system on the 
chip's surface must provide good ohmic conract and 
resist the effects of electro~n'r :ation. This paper 
w i l l  report on the effort at a ral Electric to devel- 
op reliable high-t~ mnprat~ .egnted circuits. 
That work has been and is i - . sed on both the design 
of silicon bipolar derices and th\: metallization sys- 
a em . 
SILICON I"L. -DEVICE DESIGN CONSIDERATIONS 
The operatima1 limits of 1 ~ 1 .  gates at high tern - 
peratures may be described by a variety of methods. 
Measurements of r2,ig-oscillator propgation delays 
a s  a function of current and temperature provide a 
direct indication of the operating regions with unity 
fm-in but do not provide any informati011 on noise 
margins. 
o r  one input (see Figure 1). Voltaqe measurements 
s t  the point between the gates a r e  V a  of the second 
gate's NPN transistor, with a zero input by ths switch 
and VSAT on the first gate collector with a one input. 
2 Figure 1. Measurement Method for Deterrrining 1 L 
Voltage %ins. 
Figure 2 plots the measured base-emitter for- 
wain-biased voltage drop ;or a gate input and the NPN 
collector satu-?ation voltages for a gate output a s  a 
function of temperature. During operation, the P N P  
injection forward biases the NPN base-emitter junc- 
tion and, with the collector conducting, a low (zero) 
logic level is supplied to the following stage. The 
collector sinks injection current intended for the fol- 
I ~ u ~ i n g  stage, bringin!? its input voltage down to the 
VSAT level of the collector. This turns off the fol- 
lowing stage, producing a high (one) output-logic 
level. 
50 Ian ~ s o  20n 250 3w 
A second method of determining I ~ L  operating Figure 2.  Measured NPN Base Emitter Voltage and 
limits enables an evaluation of the noise margin and Collector Saturatian Voltage versus 
signal swing. Two 1 2 ~  gates are connected in series Temperature 
with the first ~ 0 ~ e c t e d  to a switch to provide a zero 
9 7 
https://ntrs.nasa.gov/search.jsp?R=19820007459 2020-03-21T15:50:54+00:00Z
The effect d the vo::lge-swing margin may be 
observed from the data presented in Figure 2. The 
VBE for 100 PA injection current is about 550 mV at 
aborlt 125% and steadily decreases with rising tem- 
peratures to about 200 mV at +300°C . The VSAT for 
a 100 pA injection increases to a 120 mV level at 
this same temperature, resulting in a voltage noise 
margi 1 , ~ f  80 millivolts. The voltage noise margin 
may be obtained for Pie complete operating region 
from the difference between the voitages at  similar 
injection currents. 
Figure 2 indicates that signal amplitude and 
noise margin can be improved by increasing the in- 
jection -current density. 
appreciable fraction of the in:octeS; ;e current in 
the I ~ L  gate at lower temperature. The effective 
gain is forced to less than one. This also imposes a 
design rule on the gate fan-in for r given gate to per- 
form correct logical operations a t  some specified 
temperature and injection current. 
HIGH TEMPERATURE METALLIZATION 
The productiun of a stable, highly-reliable metal- 
lization system is equal in importance to the silicon 
gate design in the production of high-temperature L a .  
The metal system chosen for the high-temperature 
applications is platinum silicide/titanium-tungsten/ 
gold. 
A third method of determining I ~ L  Uiermal op- 
erating regions is provided by the digital effective 
gain, which may be measured or calculated by com- 
puter modeling techniqlles . The effective gain is 
defined a s  
collector current sinking capability 
'eff = base current removed from gate input (1). 
1 2 ~  logic signals wil l  propagate a s  long as  the digital 
effective gain is greater than one. The mechanism by 
which the effective digital gain decreases at high tem- 
peratures is through collector leakag? . The total 
leakage currents in all the OR-tied collectors (fan- 
in) connected to a gate input rob that gate of :-ome 
fraction of its injected base current and thus its 
collector-current sinking capability. This phenom - 
enon is observed in Figure 3. A s  the fan-in is  in- 
creased, the total collector leakage renloves an 
-- FAXLU - 6 
-.-.- FAPiIh - Y 
..........- TAXIS 1 10 
.-• FAXLI - I2 
i 
I- 
. 
-50 0 50 100 I50 200 2SO 300 350 
Figure 3. Modeled Temperature and Gate Fanin 
Influences on Effective Digital Gain 
Platinum silicide forms stable ohmic contacts to 
silicon, and gold was chosen for its ability to inter- 
face easily the chip to the outside world. Howe ?r, 
unlimited gold diffusing into the silicon would seri- 
ously affect device performance, and silia- .n diffusing 
into the g ~ l d  metallization can produce reliability 
problems due to the creation of voids. As a result, 
a thin titanium-tungsten barrier metal system is em- 
ployed to separate those materials. 
Verification of high reliability metallizations and 
silicon devices require accelerated aging to com - 
press time scales to reasonable durations. Since 
most failure mechanisms in integrated circuits are  
temperature dependent, an activation energy may be 
obtained for the dominant failure modes. A reaction 
rate or failure rate may then be predicted at various 
other temperatures by the Arrhenius equation: 
However, activation energies determined from high- 
temperature testinb .nay be invalid if a phase change 
has occurred. This is 2 problem that provides ron- 
siderable complications in producing high reliability 
circuits for 3000C operation; these circuits must be 
accelerated-life tested at temperatures above 350°C. 
An independent test mask was designed for metal- 
lization evaluations. The mask consists of a repeti- 
tion of the 190 x 186 mil master cell shown in Figure 
4 .  The master cell is divided by scribe lanes into 
four separable chip types. Each chip, therefore, 
'ias an area of 95 x 93 nuls. Within each chip are  
two different test element cells. Cells Al, A2, A3, 
A4, B l ,  B2, and B3 re metallization test element&. f The final cell is an I L active test circuit. 
The metallization test cells vrere designed to in- 
vestigate the electromigration effect on the thin rnetal 
layer a s  a function of the metal linewidth and metal 
line s y  :mg at elevated temperature. The electro- 
migra dn effect could eventually cause metal-line 
runoff and resulting open circuits and short circuits 
between separated metal lines. The metal test ele- 
ments were designed with a four-point probe capabil- 
ity to enable precise measurements to be made in 
order to detect effects of electromigration long before 
catastrophic failure. 
The test elements were also designed in a man- 
ner that enables ohmic contact resistance to be accu- 

ACKNOW LEDGEMSNTS 
Figure 6. Photograph of the B3 Metallization Test 
Element and the Active 121. Circuits 
CONCLUSIONS 
Integrated Injection Logic is a viable approach 
for large-scrle integrated circuits that will tolerate 
300°C. Silicon I ~ L  gate designs have been shown to 
be operable a t  these temperatures. In addition, a 
high-temperature barrier-metallization system has 
been chosen and an evaluation mask designed. Initial 
s t ress  test results are  encouraging, even thouch the 
metallization system has not been optimized. 
Device fabricltion and consultation were provided 
by L .  Cordes, C .  Pifer, 8. Vanderleest, J .  Boah 
and D . Smith. Cevice s t ress  testing and degradation 
analysis was carried oct by W .  Brouillette, W .  
Morris, ard 0. Nalin . The original 121, high-tem - 
perature work was ir-ternally funded by the General 
Electric Airwaft Engine Group, Advanced Engi- 
neering and Technology, Programs Department. 
The more recent mask design and s t ress  test evalua- 
tion was carried out under Naval Research Laboratory 
Contract N00173-79-C-0010, which is directed by 
Dr. J .E. Davey, Code 6810, and funded under Naval 
Air Systems Command sponsorship. 
REFERENCES 
D .C . Dening, L . J .  Ragonese, and C .Y. Lee, 
"Integrated Injection Logic With Extended Tem - 
perature Range Capability, " Proceedings of the 
1979 IEDM, pp. 192-195. 
L . J . Ragonese, D .C . Dening, and W .L . Morris, 
"High Temperature Extended Range Operation for 
Integrated Injection Logic circuits, " Proceedings 
of the 1980 ELECTRO, Paper 16/3. 
L . J . Ragonese and N .T . Yang, "Enhanced I ~ L  
Performance Usine Piovel Svmmetrical Cell 
Topography, " ~r&eedings-of the 1977 IEDM, 
pp. 166-169. 


High temperature LSI

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