Modern wireless System-on-Chips (SoCs), such as mobile handsets, sensor networks, and mm-wave systems, integrate an entire RF system on a single CMOS chip. Such highly complex systems require significant on-chip digital signal processing to help improve the performance of highly sensitive analog/RF components. The IC
market being competitive, the ability to achieve first pass silicon success is crucial, due to very high processing and testing time cost. Unfortunately, the ability to achieve first-pass silicon success is becoming increasingly more difficult, due to higher system complexity, higher frequency of operation, increased performance requirements, and higher process skews.
This thesis presents a 2.4 GHz, reconfigurable RF Low Noise Amplifier (LNA) using on-chip peak detection and calibration, to mitigate the deleterious effects of process, voltage and temperature (PVT) variations. The LNA can reconfigure its
input impedance matching, as well as its gain. On-chip detection of optimal input/output impedance matching is performed using an amplitude peak detector. A low power, robust maximum peak point calibration scheme is proposed that calibrates the LNA to the resonant frequency of interest. Measurement results show
that the calibration of the LNA improves the input matching (S₁₁) by a maximum of 5 dB , and power gain (S₂₁) by 3dB, while not significantly degrading the Noise Figure (NF)
