A new frequency compensation technique for output buffers able to manage a wide range of loads, is proposed in this paper. To improve the stability, this technique implements a variable zero nulling resistor in a classical Miller compensation. A replica circuit senses the operating region of the output stage and generates the required value of the nulling resistor. In order to validate the effectiveness of the proposed technique, an Internally Compensated Low Dropout (IC-LDO) regulator based on a classical topology has been chosen and designed in a 65 nm standard CMOS technology. Results show that the proposed compensation scheme improves the Phase Margin of the IC- LDO regulator keeping it higher than 54o for load currents from 0 to 100mA at the cost of increasing only 10% the total quiescent power consumption and negligible area