IC-LDO Regulator with 600 nA Quiescent Current Using a Class AB Buffer

Abstract

An ultra-low power Internally Compensated Low- Dropout (IC-LDO) regulator with a quiescent current consumption lower than 600 nA is proposed. It is based on the classical IC-LDO topology, which has been modified to include a class AB buffer between the output of the error amplifier and the gate of the pass transistor (MPASS). This way, a fast charge/discharge of its parasitic capacitance is achieved with the inherent low quiescent power consumption of class AB circuits. The proposed regulator has been fabricated in a standard 0.18- μm CMOS technology. Experimental results show that the proposed regulator has a Figure of Merit in the state of the art