Device simulation of a n-DMOS cell with trench isolation

Kamoulakos, G
Haniotakis, T
Tsiatouhas, Y
Schoellkopf, JP
and Arapoyanni, A

Device simulation of a n-DMOS cell with trench isolation

Authors: G Kamoulakos Haniotakis, T Tsiatouhas, Y Schoellkopf, JP and Arapoyanni, A
Publication date: 1 January 2001
Publisher

Abstract

The DMOS cell, a high-voltage transistor, implemented in low voltage standard 0.18 mum double-well CMOS technology with trench isolation is studied. The operation of the cell is investigated with the use of a device simulator while the effect of the trench to the operation of the cell is revealed. (C) 2000 Elsevier Science Ltd. All rights reserved

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