International Association for Cryptologic Research (IACR)
Abstract
BIKE (Bit-flipping Key Encapsulation) is a promising candidate running
in the NIST Post-Quantum Cryptography Standardization process. It is a code-based
cryptosystem that enjoys a simple definition, well-understood underlying security,
and interesting performance. The most critical step in this cryptosystem consists
of correcting errors in a QC-MDPC linear code. The BIKE team proposed variants
of the Bit-Flipping Decoder for this step for Round 1 and 2 of the standardization
process. In this paper, we propose an alternative decoder which is more friendly to
hardware implementations, leading to a latency-area performance comparable to the
literature while introducing power side channel resilience. We also show that our
design can accelerate all key generation, encapsulation and decapsulation operations
using very few common logic building blocks
