International Association for Cryptologic Research (IACR)
Abstract
Fault Template Analysis (FTA) has been shown as a powerful tool for attacking cryptosystems and exposing vulnerabilities which were previously not reported in existing literature. Fault templates can be utilized for attacking block ciphers in middle rounds
which were known prior to be resistant against
fault attacks. In this paper we revisit the potent of
fault templates and show a more systematic methodology to
develop fault templates of Boolean circuits using a
well known concept in design verification, namely
positive Davio\u27s decomposition. We show that the
improved FTAs, called FTA2.0, can be used to fault analyze
block ciphers in the middle rounds using as few as
two bit-flip faults. Further, it can be used to attack
TI-implemented block ciphers by considering a
Double Bit Upset (DBU) fault in a target share bit. The attack shows that varying the latency of the fault the adversary can
obtain unmasked bits and can recover the secret key