High  field  effect  mobility  thin  film  transistors  find 
immense  application  in  active  matrix  liquid  crystal 
display  (AMLCD)  or  active  matrix  organic  light  emitting diode (AMOLED) displays [1], [2].
Amorphous silicon  is  easily  deposited  over  large  areas  at  low  deposition  temperatures  (below  450°C)  but  it  suffers  degradation  under  bias  stress  and  under  illumination

Abhishek M.

Navneet G.

Prachi Sh.

SocioEconomic Challenges Journal (Sumy State University)

JOURNAL OF NANO- AND ELECTRONIC PHYSICS ЖУРНАЛ НАНО- ТА ЕЛЕКТРОННОЇ ФІЗИКИ 
Vol. 5 No 4, 04054(3pp) (2013) Том 5 № 4, 04054(3cc) (2013) 
 
 
2077-6772/2013/5(4)04054(3) 04054-1  2013 Sumy State University 
Modeling of Field Effect Mobility Using Grain Boundaries on  
Nanocrystalline Silicon Thin-Film Transistor (nc-Si TFT) 
 
Abhishek Mukherjee, Prachi Sharma, Navneet Gupta* 
 
Department of Electrical and Electronics Engineering,  
Birla Institute of Technology and Science, Pilani-Campus, Rajasthan, 333031 India 
 
(Received 19 July 2013; published online 31 January 2014) 
 
This work presents the effect of grain boundaries in nanocrystalline silicon thin-film transistors  
(nc-Si TFT). In this study, it is assumed that the nanocrystalline silicon film which is used as the channel 
material in TFT consists of grain boundaries perpendicular as well as parallel to the carrier flow. Analyti-
cal model for mobility due to perpendicular GBs (perp) and mobility due to parallel GBs (parallel) are devel-
oped separately and then the overall (effective) mobility, FE, is calculated incorporating both type of GBs. 
Thereafter the overall (effective) mobility µFE and drain current are plotted as a function of gate voltage. 
The trend observed from the theoretical plot of drain current versus gate voltage is in agreement with the 
experimentally observed trend.  
 
Keywords: Grain boundaries, Nanocrystalline silicon, TFT. 
 
 PACS number: 85.30.De 
 
 
                                                                
* ngupta@pilani.bits-pilani.ac.in 
1. INTRODUCTION 
 
High field effect mobility thin film transistors find 
immense application in active matrix liquid crystal 
display (AMLCD) or active matrix organic light emit-
ting diode (AMOLED) displays [1], [2]. Amorphous sili-
con is easily deposited over large areas at low deposi-
tion temperatures (below 450 C) but it suffers degra-
dation under bias stress and under illumination. To 
avoid this problem, amorphous silicon is converted to 
polycrystalline silicon using high temperature thermal 
annealing. Polycrystalline silicon is more stable but its 
fabrication requires expensive substrates due to high 
temperature processes. Nanocrystalline silicon has 
properties in between amorphous and polycrystalline 
silicon. Low temperature (below 150 ºC) deposition 
techniques have been proposed [3] for nanocrystalline 
silicon. At the same time, nanocrystalline silicon is 
much more stable than amorphous silicon due to a low-
er density of states. Thus by combining the advantages 
of both amorphous and polycrystalline silicon, nano-
crystalline silicon becomes extremely well suited for 
fabrication of thin film transistors for the applications 
described earlier. 
The effect of grain boundaries (GBs) on the carrier 
transport of polycrystalline silicon TFT have been dis-
cussed by various researchers [4-6], but the effect of 
GBs on nc-Si TFT were hardly reported [7]. 
This paper is organized as follows: In section 2, the 
modeling of transverse (perpendicular) and longitudi-
nal (parallel) GBs are reported. Section 3 provides the 
results and discussion based on the developed model. 
The last section, section 4 concludes the study given in 
the paper. 
 
2. THEORY AND MODEL 
 
Figure 1 shows the perpendicular grain boundaries 
as well as the energy band diagram along the length of 
the channel of an enhancement type n-channel device 
(p-substrate). In the figure DG is the grain size, DGB is 
the size of the grain boundary, Dd is the width of the 
depletion region (DGB  DG). The grain boundaries 
contain trap states which trap electrons, thereby lead-
ing to a reduction in effective hole concentration in the 
grain boundaries. Difference in hole concentration be-
tween the bulk and the grain boundaries leads to band 
bending at the grain boundaries. ΨB represents the 
amount of band bending at the grain boundary.  
Let RG, perp represent the resistance of a single grain, 
RGB, perp represent the resistance of a grain boundary, 
ng, perp represent the number of grains. 
 
 
 
Fig. 1 – (Top) Cross-section in presence of perpendicular 
(transverse) grain boundary. The shaded regions represent 
the grain boundaries. (Bottom) Energy band diagram along 
the length of the nanocrystalline silicon film 
 
 ABHISHEK MUKHERJEE, PRACHI SHARMA, NAVNEET GUPTA J. NANO- ELECTRON. PHYS. 5, 04054 (2013) 
 
 
04054-2 
Assuming that the grains and grain boundaries to-
gether form a series combination of resistances along 
the channel from source to drain, the total channel re-
sistance RT, perp is given by 
 
 RT, perp  ng, perp RG, perp + (ng, perp – 1) RGB, perp (1) 
 
where, ng, perp  D / DG approximately, considering that 
DGB  DG. 
 
RT, perp  
,eff perp
D
A
, RG, perp  G
G
D
A
, RGB, perp  GB
GB
D
A
 
 
Substituting these values in eq. (1), 
 
 
,eff perp
D
A
  .g perp G
G
n D
A
 + 
. .( 1)g perp GB
GB
n D
A

 (2) 
 
Let N be the hole concentration in the bulk of the 
grain. 
 
eff,perp  qNperp and G  qNG 
 
GB  (qGB)p , where „p‟ is the hole concentration in the 
GBs 
 
GB  (qGB)niexp((Ei – EF)GB / kT) 
 
        (qGB)niexp(((Ei – EF)bulk – qΨB) / kT)                
 
        (qGB)niexp((Ei – EF)bulk / kT) exp(– qΨB / kT) 
 
        (qGB)Nexp(– qΨB / kT)   (3) 
 
[Taking niexp((Ei – EF)bulk) / kT)  N, the hole con-
centration in the bulk of the grain. ni is the intrinsic 
carrier concentration]. 
where G and GB represent the mobility of the grain 
and grain boundaries respectively and G and GB rep-
resent the conductivity of the grain and grain bounda-
ries respectively. 
Now eq. (2) becomes, 
 
 
, , ,( 1)
exp
g perp G g perp G g perp GB
Bperp G
GB
n D n D n D
qAqN AqN
AqN
kT
 


 
 
 
 
 (4) 
 
Solving eq. (4) for perp we get 
 
 
 ,
,
1
1 exp
G
perp
g perp G GB B
g perp GB G
n D q
n D kT





   
   
    
 (5) 
 
where the potential barrier height is related to the gate 
voltage by [4] 
 
 
2 2
8 ( )
T si
B
s ox G T
q N t
C V V
 

 (6) 
 
where NT is the trap state density and tsi is the thickness 
of the nano crystalline silicon film, εs is the permittivity of 
silicon, Cox is the oxide capacitance per unit area. 
Now assuming that channel also consists of par-
allel (longitudinal) GBs which are shown in figure 2. 
Assuming that tG is the thickness of a single grain 
and tGB is the thickness of a grain boundary. As in 
the case of perpendicular GBs, the trapping of elec-
trons at GBs leads to reduction of hole concentration 
in the GBs, resulting in band bending at the grain 
boundaries. It is assumed that the extent of band 
bending at the GBs (ΨB) is the same as in the per-
pendicular case. 
 
 
 
Fig. 2 – Channel in presence of parallel (longitudinal) grain 
boundaries. The shaded regions represent the grain boundaries 
 
It is clear from figure 2, that the grains and grain 
boundaries form a parallel combination of resistances. 
Hence the equivalent resistance of the entire film can 
be written as  
 
 
 ,,
, , ,
11
  
g parallelg parallel
T parallel G parallel GB parallel
nn
R R R

   (7) 
 
which gives the parallel mobility as 
 
,
,
exp
1
1
1
1
B
GB GB
G G
parallel
G
GB
G GB
g parallel
g parallel
q
t
t kT
t
tt t
n
n



 
 
  
 
     
   
 
 
(8) 
 
The effective field effect mobility (µFE) can be obtained 
from the following relation 
 
 
1 1 1
FE perp parallel  
   (9) 
 
The mobility (µFE) calculated by the above model is 
used to calculate the drain current in saturation using 
the equation 
 
  
2
2
FE ox
D G T
C Z
I V V
D

   (10) 
 
3. RESULTS AND DISCUSSION  
 
Table 1 shows the typical values of the model pa-
rameters used in the calculations [8]. Figure 3 and 4 
illustrate the calculated values of effective field effect 
mobility and drain current as a function of gate volt-
age at room temperature. It is observed that effective 
field effect mobility and hence the drain current in-
creases rapidly with the increase in gate voltage 
which is due to the gate-induced barrier lowering ef-
fects. Also as N increases, barrier potential will de-
 MODELING OF FIELD EFFECT MOBILITY USING GRAIN BOUNDARIES… J. NANO- ELECTRON. PHYS. 5, 04054 (2013) 
 
 
04054-3 
crease. This means that available carriers for 
transport will increase hence it decreases the trap 
states at the oxide-silicon interface of nc-Si TFT. This 
effect results in an increase in the channel mobility 
which in turn increases the drain current. 
Figure 5 shows the experimental values of drain 
current versus gate voltage taken from Teng and  
Anderson [8] in saturation region and at a drain volt-
age, VD  9 V. 
 
Table 1 – Parameters used in the study [8] 
 
Parameters Values 
DGB / DG 0.1 
tGB / tG 0.1 
G 203 cm2/V-s 
GB 0.3 cm2/V-s 
tSi 90 nm 
DG 25 nm 
tG 25 nm 
Z / D 200 m / 25 µm 
tox 150 nm 
VT 3 V 
 
 
 
Fig. 3 – Computed variation of field effect mobility with gate 
voltage at room temperature 
 
It is observed that the trend of the experimental 
values are same as that of the computed values using 
developed analytical model, however the deviation from 
the actual values are attributed due to the fact that the 
actual device may have affected from various other 
effects such as channel length modulation, drain in-
duced barrier lowering and impact ionization which 
may be further incorporated to strengthen the present 
model. 
 
 
 
 
Fig. 4 – Computed variation of drain current with gate voltage 
at room temperature 
 
 
 
Fig. 5 – Experimental variation of drain current with gate 
voltage at room temperature [8] 
 
4. CONCLUSION 
 
This work proposed the development of an analyti-
cal mobility model for nanocrystalline silicon thin film 
transistors considering the effects of perpendicular and 
parallel GBs. The mobility is then used to calculate the 
drain current. The trend obtained is in agreement with 
the experimentally observed trend.  
REFERENCES 
 
1. Y. Nakata, T. Itoga, T. Okamoto, T. Hamada, Y. Ishii, 
Sharp Tech. J. No 3 (2001). 
2. Hyun Jung Lee, Thesis on “Top-Gate Nanocrystalline Sili-
con Thin Film Transistors” (University of Waterloo: On-
tario, Canada: 2008). 
3. D. Dosev, B. Inıguez, L.F. Marsal, J. Pallares, T. Ytterdal, 
Solid-State Electron. 47, 1917 (2003). 
4. N. Gupta, B.P. Tyagi, Indian J. Pure Appl. Phys. 42, 528 
(2004). 
5. N. Gupta, B.P. Tyagi, Indian J Eng. Mater. Sci. 13, 145 
(2006). 
6. H. Hao, M. Wang, B. Zhang, X. Shi, M. Wong, J. Appl. 
Phys. 103, 094513 (2008). 
7. H. Xueli, Thesis “Thin Film Transistors Using Nanocrys-
talline Silicon from Metal Induced Growth” (State Univer-
sity of New York at Buffalo: 2012). 
8. L.H. Teng, W.A. Anderson, Solid-State Electron. 48, 309 
(2004).
 


Modeling of Field Effect Mobility Using Grain Boundaries on Nanocrystalline Silicon Thin-Film Transistor (nc-Si TFT)

Electronic Sumy State University Institutional Repository

JOURNAL OF NANO- AND ELECTRONIC PHYSICS ЖУРНАЛ НАНО- ТА ЕЛЕКТРОННОЇ ФІЗИКИ Vol. 5 No 4, 04054(3pp) (2013) Том 5 № 4, 04054(3cc) (2013)   2077-6772/2013/5(4)04054(3) 04054-1  2013 Sumy State University Modeling of Field Effect Mobility Using Grain Boundaries on  Nanocrystalline Silicon Thin-Film Transistor (nc-Si TFT)  Abhishek Mukherjee, Prachi Sharma, Navneet Gupta*  Department of Electrical and Electronics Engineering,  Birla Institute of Technology and Science, Pilani-Campus, Rajasthan, 333031 India  (Received 19 July 2013; published online 31 January 2014)  This work presents the effect of grain boundaries in nanocrystalline silicon thin-film transistors  (nc-Si TFT). In this study, it is assumed that the nanocrystalline silicon film which is used as the channel material in TFT consists of grain boundaries perpendicular as well as parallel to the carrier flow. Analyti-cal model for mobility due to perpendicular GBs (perp) and mobility due to parallel GBs (parallel) are devel-oped separately and then the overall (effective) mobility, FE, is calculated incorporating both type of GBs. Thereafter the overall (effective) mobility µFE and drain current are plotted as a function of gate voltage. The trend observed from the theoretical plot of drain current versus gate voltage is in agreement with the experimentally observed trend.   Keywords: Grain boundaries, Nanocrystalline silicon, TFT.   PACS number: 85.30.De                                                                   * ngupta@pilani.bits-pilani.ac.in 1. INTRODUCTION  High field effect mobility thin film transistors find immense application in active matrix liquid crystal display (AMLCD) or active matrix organic light emit-ting diode (AMOLED) displays [1], [2]. Amorphous sili-con is easily deposited over large areas at low deposi-tion temperatures (below 450 C) but it suffers degra-dation under bias stress and under illumination. To avoid this problem, amorphous silicon is converted to polycrystalline silicon using high temperature thermal annealing. Polycrystalline silicon is more stable but its fabrication requires expensive substrates due to high temperature processes. Nanocrystalline silicon has properties in between amorphous and polycrystalline silicon. Low temperature (below 150 ºC) deposition techniques have been proposed [3] for nanocrystalline silicon. At the same time, nanocrystalline silicon is much more stable than amorphous silicon due to a low-er density of states. Thus by combining the advantages of both amorphous and polycrystalline silicon, nano-crystalline silicon becomes extremely well suited for fabrication of thin film transistors for the applications described earlier. The effect of grain boundaries (GBs) on the carrier transport of polycrystalline silicon TFT have been dis-cussed by various researchers [4-6], but the effect of GBs on nc-Si TFT were hardly reported [7]. This paper is organized as follows: In section 2, the modeling of transverse (perpendicular) and longitudi-nal (parallel) GBs are reported. Section 3 provides the results and discussion based on the developed model. The last section, section 4 concludes the study given in the paper.  2. THEORY AND MODEL  Figure 1 shows the perpendicular grain boundaries as well as the energy band diagram along the length of the channel of an enhancement type n-channel device (p-substrate). In the figure DG is the grain size, DGB is the size of the grain boundary, Dd is the width of the depletion region (DGB  DG). The grain boundaries contain trap states which trap electrons, thereby lead-ing to a reduction in effective hole concentration in the grain boundaries. Difference in hole concentration be-tween the bulk and the grain boundaries leads to band bending at the grain boundaries. ΨB represents the amount of band bending at the grain boundary.  Let RG, perp represent the resistance of a single grain, RGB, perp represent the resistance of a grain boundary, ng, perp represent the number of grains.    Fig. 1 – (Top) Cross-section in presence of perpendicular (transverse) grain boundary. The shaded regions represent the grain boundaries. (Bottom) Energy band diagram along the length of the nanocrystalline silicon film   ABHISHEK MUKHERJEE, PRACHI SHARMA, NAVNEET GUPTA J. NANO- ELECTRON. PHYS. 5, 04054 (2013)   04054-2 Assuming that the grains and grain boundaries to-gether form a series combination of resistances along the channel from source to drain, the total channel re-sistance RT, perp is given by   RT, perp  ng, perp RG, perp + (ng, perp – 1) RGB, perp (1)  where, ng, perp  D / DG approximately, considering that DGB  DG.  RT, perp  ,eff perpDA, RG, perp  GGDA, RGB, perp  GBGBDA  Substituting these values in eq. (1),   ,eff perpDA  .g perp GGn DA + . .( 1)g perp GBGBn DA (2)  Let N be the hole concentration in the bulk of the grain.  eff,perp  qNperp and G  qNG  GB  (qGB)p , where „p‟ is the hole concentration in the GBs  GB  (qGB)niexp((Ei – EF)GB / kT)          (qGB)niexp(((Ei – EF)bulk – qΨB) / kT)                         (qGB)niexp((Ei – EF)bulk / kT) exp(– qΨB / kT)          (qGB)Nexp(– qΨB / kT)   (3)  [Taking niexp((Ei – EF)bulk) / kT)  N, the hole con-centration in the bulk of the grain. ni is the intrinsic carrier concentration]. where G and GB represent the mobility of the grain and grain boundaries respectively and G and GB rep-resent the conductivity of the grain and grain bounda-ries respectively. Now eq. (2) becomes,   , , ,( 1)expg perp G g perp G g perp GBBperp GGBn D n D n DqAqN AqNAqNkT      (4)  Solving eq. (4) for perp we get    ,,11 expGperpg perp G GB Bg perp GB Gn D qn D kT           (5)  where the potential barrier height is related to the gate voltage by [4]   2 28 ( )T siBs ox G Tq N tC V V  (6)  where NT is the trap state density and tsi is the thickness of the nano crystalline silicon film, εs is the permittivity of silicon, Cox is the oxide capacitance per unit area. Now assuming that channel also consists of par-allel (longitudinal) GBs which are shown in figure 2. Assuming that tG is the thickness of a single grain and tGB is the thickness of a grain boundary. As in the case of perpendicular GBs, the trapping of elec-trons at GBs leads to reduction of hole concentration in the GBs, resulting in band bending at the grain boundaries. It is assumed that the extent of band bending at the GBs (ΨB) is the same as in the per-pendicular case.    Fig. 2 – Channel in presence of parallel (longitudinal) grain boundaries. The shaded regions represent the grain boundaries  It is clear from figure 2, that the grains and grain boundaries form a parallel combination of resistances. Hence the equivalent resistance of the entire film can be written as     ,,, , ,11  g parallelg parallelT parallel G parallel GB parallelnnR R R   (7)  which gives the parallel mobility as  ,,exp1111BGB GBG GparallelGGBG GBg parallelg parallelqtt kTttt tnn               (8)  The effective field effect mobility (µFE) can be obtained from the following relation   1 1 1FE perp parallel     (9)  The mobility (µFE) calculated by the above model is used to calculate the drain current in saturation using the equation    22FE oxD G TC ZI V VD   (10)  3. RESULTS AND DISCUSSION   Table 1 shows the typical values of the model pa-rameters used in the calculations [8]. Figure 3 and 4 illustrate the calculated values of effective field effect mobility and drain current as a function of gate volt-age at room temperature. It is observed that effective field effect mobility and hence the drain current in-creases rapidly with the increase in gate voltage which is due to the gate-induced barrier lowering ef-fects. Also as N increases, barrier potential will de- MODELING OF FIELD EFFECT MOBILITY USING GRAIN BOUNDARIES… J. NANO- ELECTRON. PHYS. 5, 04054 (2013)   04054-3 crease. This means that available carriers for transport will increase hence it decreases the trap states at the oxide-silicon interface of nc-Si TFT. This effect results in an increase in the channel mobility which in turn increases the drain current. Figure 5 shows the experimental values of drain current versus gate voltage taken from Teng and  Anderson [8] in saturation region and at a drain volt-age, VD  9 V.  Table 1 – Parameters used in the study [8]  Parameters Values DGB / DG 0.1 tGB / tG 0.1 G 203 cm2/V-s GB 0.3 cm2/V-s tSi 90 nm DG 25 nm tG 25 nm Z / D 200 m / 25 µm tox 150 nm VT 3 V    Fig. 3 – Computed variation of field effect mobility with gate voltage at room temperature  It is observed that the trend of the experimental values are same as that of the computed values using developed analytical model, however the deviation from the actual values are attributed due to the fact that the actual device may have affected from various other effects such as channel length modulation, drain in-duced barrier lowering and impact ionization which may be further incorporated to strengthen the present model.     Fig. 4 – Computed variation of drain current with gate voltage at room temperature    Fig. 5 – Experimental variation of drain current with gate voltage at room temperature [8]  4. CONCLUSION  This work proposed the development of an analyti-cal mobility model for nanocrystalline silicon thin film transistors considering the effects of perpendicular and parallel GBs. The mobility is then used to calculate the drain current. The trend obtained is in agreement with the experimentally observed trend.  REFERENCES  1. Y. Nakata, T. Itoga, T. Okamoto, T. Hamada, Y. Ishii, Sharp Tech. J. No 3 (2001). 2. Hyun Jung Lee, Thesis on “Top-Gate Nanocrystalline Sili-con Thin Film Transistors” (University of Waterloo: On-tario, Canada: 2008). 3. D. Dosev, B. Inıguez, L.F. Marsal, J. Pallares, T. Ytterdal, Solid-State Electron. 47, 1917 (2003). 4. N. Gupta, B.P. Tyagi, Indian J. Pure Appl. Phys. 42, 528 (2004). 5. N. Gupta, B.P. Tyagi, Indian J Eng. Mater. Sci. 13, 145 (2006). 6. H. Hao, M. Wang, B. Zhang, X. Shi, M. Wong, J. Appl. Phys. 103, 094513 (2008). 7. H. Xueli, Thesis “Thin Film Transistors Using Nanocrys-talline Silicon from Metal Induced Growth” (State Univer-sity of New York at Buffalo: 2012). 8. L.H. Teng, W.A. Anderson, Solid-State Electron. 48, 309 (2004). 

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Modeling of Field Effect Mobility Using Grain Boundaries on Nanocrystalline Silicon Thin-Film Transistor (nc-Si TFT)

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