It has been a constant challenge in wireless system design to meet the growing demand for an ever higher data rate and more diversified functionality at minimal cost and power consumption. The key lies in exploiting the phenomenal success of CMOS technology scaling for high-level integration. This underlies the paradigm shift in the field of integrated circuit (IC) design to one that increasingly favours digital circuits as opposed to their analog counterparts. With radio transceiver design for wireless systems in particular, a noticeable trend is the introduction of digital-intensive solutions for traditional analog functions. A prominent example is the emergence of the all-digital phase-locked loop (ADPLL) architectures for frequency synthesis. By avoiding traditional analog blocks, the ADPLL brings the benefits of high-level integration and improved programmability.
This thesis presents ADPLL frequency synthesizer design, highlighting practical design considerations and technical innovations. Three prototype designs using a 65-nm CMOS technology are presented. The first example address a low-power ADPLL design for 2.4-GHz ISM (Industrial, Scientific, Medical) band frequency synthesis. A high-speed topology is employed in the implementation for the variable phase accumulator to count full cycles of the radio frequency (RF) output. A simple technique based on a short delay line in the reference signal path allows the time-to-digital converter (TDC) core to operate at a low duty cycle with approximately 95% reduction in its average power consumption. The ADPLL incorporates a two-point modulation scheme with an adaptive gain calibration to allow for direct frequency modulation. The second implementation is a wide-band ADPLL-based frequency synthesizer for cognitive radio sensor units. It employs a digitally controlled ring oscillator with an LC tank introduced to extend the tuning range and reduce power dissipation. An adaptive frequency calibration technique based on binary search is used for fast frequency settling. The third implementation is another wideband ADPLL frequency synthesizer. At the architectural level, separation of coarse-tune and fine-tune branches results in a word length reduction for both of them and allows the coarse tuning logic to be powered off or clock gated during normal operation, which led to a significant reduction in the area and power consumption for the digital logic and simplified the digital design. A dynamic binary search technique was proposed to achieve further improved frequency calibration speed compared with previous techniques. In addition, an original technique was employed for the frequency tuning of the wideband ring oscillator to allow for compact design and excellent linearity
