Deakin, Callum

Liu, Zhixin

English

UCL Discovery

Power dissipation bounds for photonic analog todigital convertersCallum Deakin, Zhixin LiuDepartment of Electronic and Electrical Engineering, University College London, London, U.K.callum.deakin.17@ucl.ac.uk, zhixin.liu@ucl.ac.ukAbstract: We present the first power dissipation bounds for a generalised class of photonicanalog to digital converters, and estimate their achievable power efficiency compared toconventional electronic designs. © 2022 The Author(s)1. IntroductionAnalog to digital converters (ADCs) are ubiquitous devices found in any system that requires the digital processingor storage of continuous time signals. The speed, accuracy and efficiency of ADCs can profoundly impact systemarchitectures and overall performance across a huge variety of applications, including optical and wireless com-munications, electronic warfare, medical imaging, and instrumentation. In optical and wireless communicationssystems, the accuracy of the high speed (> 1 GHz) ADCs required to digitise high baudrate signals is often limitedby clock jitter or comparator ambiguity, which can limit spectral efficiency and modulation format flexibility.This well known trade-off between sampling speed and digitisation accuracy, characterised by signal to noiseratio (SNR) or effective number of bits (ENOB), is a key challenge in ADC design. Many have proposed photonicdesigns to combat this trade-off [1]: optics based samplers and converters that exploit the high bandwidth and lowjitter of optical sources, with a wide variety of published photonic ADC architectures demonstrating performancewell in excess of state of the art electronic ADCs (e.g. 7 bits ENOB at 40 GHz [2, 3]). Despite this impressiveperformance there has been, to the best of our knowledge, little to no discussion of the power efficiency of photonicADCs. Power dissipation and efficiency are critical factors in determining the performance of ADCs, especially incommunications systems that are designed to minimise the energy consumption or cost per bit transmitted [4, 5].Therefore, assessing the power consumption and efficiency is essential to determining whether the impressivespeed-resolution performance afforded by photonic ADCs can translate into real-world improvements in networkcapacity and efficiency in energy sensitive applications [6].In this paper, we derive lower bounds on the power consumption of photonic ADCs. We discuss how the mainactive components required to implement a photonic ADC impact the overall energy per sample, and compare thepower efficiency performance of common photonic ADCs to conventional electronic ADCs in terms of the widelyused Schreier figure of merit, FOMS =∆ f×SNRP [4, 7], for Nyquist bandwidth ∆ f and power consumption P.2. Power dissipation boundsAlthough photonic ADCs have been demonstrated with a wide variety of architectures [1], most of the best per-forming designs can be described as a variation of the generalised model shown in Fig. 1(a) [2, 3, 9, 10]. Thismodel is generalised in the sense that it contains the minimum active components required to implement a pho-tonic ADC: a pulsed laser source as the optical sampling device, an electro-optic modulator to map the input signalonto the optical pulse train, followed by a bank of N channels containing a photoreceiver and electronic sub-ADCDSPPulsed laser sourceModulatorDEMUXN channelsOptical sourceSub-receiverEO conversionOpticsAnalog electronicsADC Full rate digital outputInput signaltDSPDigital electronicsADCVFSVbiasPopt(b)(a)Fig. 1. (a) Generalised model of a photonic ADC, with principal active components highlighted in orange. (b) Sub-receivermodel: the illuminated photodiode switches an ADC input, represented as a capacitive load, to the full scale voltage VFS [8].1that detect subsets (either in the time [2, 9] or frequency [3, 10] domains) of the incoming signal in parallel at afraction of the aggregate sampling rate. The signal is then reconstructed digitally to obtain the full rate signal at themuch higher resolution offered by such optical techniques. The power consumption contribution of the requiredrestitching digital signal processing (DSP) is not considered here since it is the same for interleaving electronicADCs, which are the most common designs at high sampling rates, so is not relevant for comparison.Considering the highlighted active components in Fig. 1, we can derive an expression for the energy per sampleof a photonic ADC digitising an input signal defined only by its peak to average power ratio (PAPR)P/ fs =Poptfs[4π2RVbiasPAPR︸ ︷︷ ︸sub-receiver+1ηWPE︸ ︷︷ ︸laser source]+fsV 2∆ f4Z0 ×PAPR︸ ︷︷ ︸modulator(1)for sampling rate fs = 2∆ f , photodiode responsivity R, photodiode bias Vbias, laser wall plug efficiency ηWPE. Themodulator is assumed to be a travelling wave Mach-Zehnder modulator of input impedance Z0 and Vπ = ∆ fV∆ f ,where V∆ f is the modulator Vπ per Hz bandwidth (in volts per Hz), which is driven such that the peak value of theinput signal is equal to the full modulation depth of the modulator (hence the PAPR factor in (1)). It is assumedthat the modulator nonlinearity can be compensated through simple digital compensation [11]: the factor 4π2comes from the linearized modulator transfer function. Note that actual photonic ADCs will contain additionalpassive components: e.g. a pulse interleaver [2], filters and gratings [10] or dispersive elements [9] that are notshown in the generalised model of Fig. 1. In terms of power consumption, the effect of these passive componentsis to simply reduce the effective wall plug efficiency of the optical source. Some may even have multiple opticalsources [3, 10], which will simply increase the value of the optical power term.The required optical source power Popt is set by the power required to achieve a desired SNR, given the noiselimits set by shot and thermal noise for optical frequency ν and Planck constant hPopt/ fs =PAPR4π2[hν2×SNR︸ ︷︷ ︸shot noise+R√CRx8kBT ×SNR︸ ︷︷ ︸thermal noise]. (2)Here, the thermal noise floor is set by the minimum optical energy to switch a capacitive load CRx at the desiredSNR within a single sampling period, including the photodiode junction capacitance, as shown in Fig. 1(b) [8].The best performing photonic ADCs are usually (or designed to be) jitter limited, in which case the SNR followsthe well known upper bound of SNR = (2πσ fin)−2 for root-mean-square jitter σ and input frequency fin.Fig. 2(a) plots the modulator energy per sample as a function of fs (assuming Nyquist rate sampling) for PAPR=3 dB (i.e. a sine wave). Although 10 GHz/V is typical for commercially available modulators, recent results havedemonstrated modulators approaching 100 GHz/V performance [12], which Fig. 2(a) shows has a potential tosignificantly reduce the energy per sample. Also plotted is the thermal noise limited sub-ADC power consumptionin the scenario that the ADC is jitter limited: note here that energy per sample increases with improved jitter, sincemore accurate sub-ADC digitisation is needed to detect the higher SNR signal. On the other hand, increasingfrequency for a fixed jitter decreases the power consumption as the SNR decreases. Fig. 2(b) shows how a higherSNR increases the energy per sample due to the increase in optical power needed to overcome shot and thermal106 107 108 109 1010 1011 101210−1010−1210−1410−1610 GHz/V100 fs33 GHz/V100GHz/V10 fs1 fs(a)fs (Hz)Energypersample(J) ModulatorJitter10 20 30 40 50 60 70 80ShotThermal(b)SNR (dB)10%, 100 fF0.1%, 1 pFFig. 2. (a) Modulator and jitter limited energy per sample scaling with fs. (b) Optical power limited energy per sample scalingwith SNR: dashed and dotted lines indicate the shot and thermal noise limits respectively for each case. For all cases in bothplots: Z0 = 50 Ω, Vbias = 3 V, R = 1 A/W, ν = 192 THz, T = 300 K.2106 107 108 109 1010 1011 1012120140160180fs (Hz)FOMS(dB) [2][9][10][3]Electronic ADCs [14]Photonic ADCs [2, 3, 9, 10](b)Parameter Worst Best1/V∆ f 10 GHz/V 100 GHz/VJitter 1 ps 1 fsLoss 20 dB 0 dBPAPR 10 dB 3 dBZ0 50 50ηWPE 1% 10%R 0.5 A/W 1.25 A/WVbias 3 V 1 VCRx 1 pF 100 fFFig. 3. (a) FOMS estimation for photonic ADCs (red circles) compared to published results from electronic ADCs [14]. Thered shaded area indicates the achievable FOMS for generalised photonic ADCs based on (1)/(2) and the parameters in (b).The red arrows extending from the photonic ADC results indicate the maximum estimated FOMS for each architecture.noise, as per (2). Two cases are plotted: {ηWPE = 0.1 %, CRx = 1 pF} (blue) and {ηWPE = 10 %, CRx = 100 fF}(red) with the limits imposed by shot and thermal noise indicated for each case. Clearly, shot and thermal noiselimit are the dominant contributions to the energy per sample for high and low SNR respectively. Recent resultshave demonstrated microcomb sources with wall plug efficiencies up to 3.4% [13].3. Power efficiency comparison with electronic ADCsWe also estimate a range for the achievable FOMS in Fig. 3(a). The red shaded region indicates the achievableFOMS for photonic ADCs calculated from (1)/(2) based on the best and the worst case parameters in Fig. 3(b). Theblue dots are the measured FOMS from published electronic ADC results [14]. Red circles indicate the estimatedFOMS for various photonic ADCs, based on the published frequency/SNR result and best estimates of the powerconsumption of the components used. Since these published photonic ADCs results were likely designed withoutregard for power consumption, we have also estimated the maximum achievable FOMS based on the minimumestimated power (using the ‘best’ parameters in Fig. 3(b)) required to achieve the presented result, which is in-dicated using an arrow for each result. While even in the best scenario our estimates for photonic ADCs FOMSbarely exceeds published electronic ADC results for fs < 108 Hz, the red shaded area in Fig. 3(a) clearly indicatesthat photonic ADCs may outperform their electronic ADC counterparts on an FOMS basis at higher frequenciesdue to their superior jitter performance.4. ConclusionWe model and estimate the power consumption lower bounds of photonic ADCs and compare them with electronicADCs for the first time. We show that photonic ADCs may outperform electronic ADCs on a FOMS basis in high( fs > 1010 Hz) frequency scenarios due to their superior jitter performance. Note that the results presented hereare theoretical bounds, which represent the best achievable results for practical designs.References1. G. C. Valley, “Photonic analog-to-digital converters,” Opt. Express 15, 1955–1982 (2007).2. A. Khilo et al., “Photonic ADC: overcoming the bottleneck of electronic jitter,” Opt. Express 20, 4454–4469 (2012).3. C. Deakin and Z. Liu, “Frequency interleaving dual comb photonic ADC with 7 bits ENOB up to 40 GHz,” in CLEO: Science andInnovations, (Optica Publishing Group, 2022), pp. STh5M–1.4. B. Murmann, “A/D converter trends: Power dissipation, scaling and digitally assisted architectures,” in 2008 IEEE Custom IntegratedCircuits Conference, (IEEE, 2008), pp. 105–112.5. B. Razavi, “Design considerations for interleaved ADCs,” IEEE J. Solid-State Circuits 48, 1806–1817 (2013).6. R. S. Tucker, “Green optical communications—Part I: Energy limitations in transport,” IEEE J. Sel. Top. Q. Elec. 17, 245–260 (2010).7. S. Pavan, R. Schreier, and G. C. Temes, Understanding Delta-Sigma Data Converters (IEEE Press, 2017).8. D. A. Miller, “Attojoule optoelectronics for low-energy information processing and communications,” J. Light. T. 35, 346–396 (2017).9. S. Gupta and B. Jalali, “Time-warp correction and calibration in photonic time-stretch analog-to-digital converter,” Opt. Lett. 33,2674–2676 (2008).10. D. Fang et al., “320 GHz analog-to-digital converter exploiting kerr soliton combs and photonic-electronic spectral stitching,” in 2021European Conference on Optical Communication (ECOC), (IEEE, 2021), pp. Th3C1–PD2.2.11. T. Clark, M. Currie, and P. Matthews, “Digitally linearized wide-band photonic link,” J. Light. T. 19, 172–179 (2001).12. C. Wang et al., “Integrated lithium niobate electro-optic modulators operating at CMOS-compatible voltages,” Nature 562, 101–104(2018).13. B. Stern et al., “Battery-operated integrated frequency comb generator,” Nature 562, 401–405 (2018).14. B. Murmann, “ADC performance survey 1997-2022,” http://web.stanford.edu/˜murmann/adcsurvey. [Online].3

Power dissipation bounds for photonic analog to digital converters

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Power dissipation bounds for photonic analog to digital converters

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