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SystemVerilog for design: a guide to using systemverilog for hardware design and modeling
Authors
Simon Davidmann
Peter Flake
Stuart Sutherland
Publication date
1 January 2003
Publisher
'Springer Fachmedien Wiesbaden GmbH'
Abstract
Abstract is not available.
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oai:cds.cern.ch:2756801
Last time updated on 21/03/2021