The global need to reduce dependence on fossil fuels for electricity production has become an ongoing research theme in the last decade. Clean energy sources (such as wind energy and solar energy) have considerable potential to reduce reliance on fossil fuels and mitigate climate change. However, wind energy is going to become more mainstream due to technological advancement and geographical availability. Therefore, various technologies exist to maximize the inherent advantages of using wind energy conversion systems (WECSs) to generate electrical power. One important technology is the power electronics interface that enables the transfer and effective control of electrical power from the renewable energy source to the grid through the filter and isolation transformer. However, the transformer is bulky, generates losses, and is also very costly. Therefore, the term "transformer-less connection" refers to eliminating a step-up transformer from the WECS, while the power conversion stage performs the conventional functions of a transformer. Existing power converter configurations for transformer-less connection of a WECS are either based on the generator-converter configuration or three-stage power converter configuration. These configurations consist of conventional multilevel converter topologies and two-stage power conversion between the generator-side converter topology and the high-order filter connected to the collection point of the wind power plant (WPP). Thus, the complexity and cost of these existing configurations are significant at higher voltage and power ratings. Therefore, a single-stage multilevel converter topology is proposed to simplify the power conversion stage of a transformer-less WECS. Furthermore, the primary design challenges โ such as multiple clamping devices, multiple dc-link capacitors, and series-connected power semiconductor devices โ have been mitigated by the proposed converter topology. The proposed converter topology, known as the "tapped inductor quasi-Z-source nested neutral-point-clamped (NNPC) converter," has been analyzed, and designed, and a prototype of the topology developed for experimental verification. A field-programmable gate array (FPGA)-based modulation technique and voltage balancing control technique for maintaining the clamping capacitor voltages was developed. Hence, the proposed converter topology presents a single-stage power conversion configuration. Efficiency analysis of the proposed converter topology has been studied and compared to the intermediate and grid-side converter topology of a three-stage power converter configuration. A direct current (DC) component minimization technique to minimize the dc component generated by the proposed converter topology was investigated, developed, and verified experimentally. The proposed dc component minimization technique consists of a sensing and measurement circuitry with a digital notch filter. This thesis presents a detailed and comprehensive overview of the existing power converter configurations developed for transformer-less WECS applications. Based on the developed 2 comparative benchmark factor (CBF), the merits and demerits of each power converter configuration in terms of the component counts and grid compliance have been presented. In terms of cost comparison, the three-stage power converter configuration is more cost-effective than the generatorconverter configuration. Furthermore, the cost-benefit analysis of deploying a transformer-less WECSs in a WPP is evaluated and compared with conventional WECS in a WPP based on power converter configurations and collection system. Overall, the total cost of the collection system of WPP with transformer-less WECSs is about 23% less than the total cost of WPP with conventional WECs. The derivation and theoretical analysis of the proposed five-level tapped inductor quasi-Z-source NNPC converter topology have been presented, emphasizing its operating principles, steady-state analysis, and deriving equations to calculate its inductance and capacitance values. Furthermore, the FPGA implementation of the proposed converter topology was verified experimentally with a developed prototype of the topology. The efficiency of the proposed converter topology has been evaluated by varying the switching frequency and loads. Furthermore, the proposed converter topology is more efficient than the five-level DC-DC converter with a five-level diode-clamped converter (DCC) topology under the three-stage power converter configuration. Also, the cost analysis of the proposed converter topology and the conventional converter topology shows that it is more economical to deploy the proposed converter topology at the grid side of a transformer-less WECS
