A synchronous architecture for the L0 muon trigger

Abstract

In this note we describe a new implementation for the L0 muon trigger. It is based on a fully synchronous and pipeline architecture. The 25920 logical pads and strips data, produced by the muon detector, are sent at once to the muon trigger. The data transfer is performed at a frequency of 40 MHz and relies on ~1250 high speed optical links running at 1.6 Gb/s. The muon trigger processor is distributed over 4 crates. Each of them is connected to a quarter of the muon system. The implementation is based on a unique processing board. Data transfers between boards are performed at 80 MHz via a custom backplane running only point to point connections. Synchronization between data and the bunch crossing identifier is preserved during the whole processing cycle. In this note, we present the data flow, hardware implementation, latency and cost estimate