The Level-1 Global Trigger for Phase-2 Algorithms, configuration and integration in the CMS offline framework

Abstract

For the High-Luminosity Large Hadron Collider (HL-LHC) operation, the Compact Muon Solenoid will undergo a significant upgrade and redesign. An upgraded Level-1 Trigger system, based on multiple types of custom processing boards equipped with Xilinx Ultrascale+ Field Programmable Gate Arrays (FPGAs), will exploit fine grained information from the detector subsystems (calorimeter, muon systems and the silicon-strip tracker). The final stage of the Level-1 Trigger, the Phase-2 Global Trigger (P2GT), will receive more than 20 different trigger object collections from upstream systems and will be able to evaluate about 1000 cut-based and machine learning algorithms distributed over up to twelve boards. The P2GT is designed as a modular system with an easily re-configurable firmware, designed to meet the demand of high flexibility required for adapting trigger strategies during operation of the HL-LHC. The algorithms are kept highly configurable and tools are provided to allow their study, verification, and emulation from within the CMS offline software framework (CMSSW) without the need for knowledge of the underlying firmware implementation. A tool has been developed that converts the Python-based configuration used by CMSSW into VHDL for use in the hardware trigger. A prototype firmware for a single Global Trigger board has been developed, which includes de-multiplexing logic, conversion to an internal common object format and distribution of the data over the FPGA. In this framework, 197 algorithms are implemented at a clock speed of 480 MHz. The prototype has been thoroughly tested and verified using the CMSSW emulator. The P2GT is presented with the novel integration within CMSSW and streamlined translation into VHDL code