Pre-Production Testing of the HCCStar at Penn for the ATLAS ITk Detector

Abstract

The high-luminosity LHC requires a complete overhaul of the ATLAS inner tracker subsystem, including a new silicon-strip charged-particle tracking detector. The HCCStar (Hybrid Controller Chip) is one of three new radiation-tolerant ASICs for this subsystem. As the interface to multiple binary readout ASICs for the strip detector, the HCCStar buffers and forwards controls signals and trigger and readout requests to them, and serializes their output at 640 MHz. All HCCStars undergo a suite of tests to verify their analog and digital functionality, and large statistics of performance with various operational parameters are collected