Campagnolo, R

Esteve-Bosch, R

Helstrup, H

Jiménez de Parga, A

Lien, J A

Mota, B

Musa, L

Röhrich, D

Skaali, B

Ullaland, K

Vestbø, A S

Wormald, D

CERN Document Server

Readout Control Unit of the Front End Electronics for the ALICE Time ProjectionChamberR. Esteve Bosch[1], R. Campagnolo[1], H. Helstrup[3], A. Jiménez de Parga [1], J. A. Lien[1,2,3],B. Mota[1], L. Musa[1], D. Röhrich[2], B. Skaali[4], K. Ullaland[2], A. S. Vestbø[2], D. Wormald[4]for the ALICE Collaboration[1] CERN, Geneva, Switzerland, [2] University of Bergen, Bergen, Norway, [3] Høgskolen i Bergen, Bergen, Norway, [4]University of Oslo, Oslo, NorwayAbstractThe readout electronics for the ALICE TPC detectorconsists of 4356 front-end cards (FECs) that contain thecomplete chain to readout the signals coming from 570132pads. The front-end cards are grouped in 216 readoutpartitions, each controlled by a Readout Control Unit (RCU)that interfaces the FECs to the DAQ, the Trigger, and theDetector Control System. The RCU broadcast the triggerinformation to the FECs, collects the trigger related data fromthe FECs, assembles a sub-event, compresses the data andsends the compressed packed sub-event to the DAQ via theALICE Detector Data Link (DDL). The RCU is designed tocope with a maximum data throughput of 200 Mbyte/s. In thispaper we present an overview of the requirements, thearchitecture and some of the main design features of the RCU,as well as a description of two RCU prototypes.  I. INTRODUCTIONThe ALICE Time Projection Chamber [1] (TPC) is a largegas cylinder (88 m3) divided in two drift regions by a centralelectrode located at its axial centre. A field cage creates auniform electric field along each half of the chamber. Chargedparticles traversing the TPC volume ionise the gas along theirpath, liberating electrons that drift towards the detector endplates where multi-wire proportional chambers, with cathodepad readout, provide the necessary signal amplification. Eachof the two readout planes is azimuthally segmented in 18trapezoidal sectors.The front-end electronics [2] for the ALICE TPC consistsof 570132 channels. A single readout channel is comprised ofthree basic functional units: 1) a charge sensitive shapingamplifier, which transforms the charge induced in the pad intoa differential semi-gaussian signal; 2) a 10-bit 10-MSPS A/Dconverter; 3) a digital circuit that contains a shortening filterfor the cancellation of the signal tail, the baseline subtractionand zero suppression circuits, and a multi-event memory. Theanalogue functions are implemented by a custom integratedcircuit (PASA) that incorporates in a single chip 16 channels.The ADC and the digital circuits (for 16 channels) arecontained in a single chip named ALTRO (ALICE TPC ReadOut) [3]. The maximum number of samples that can becontinuously processed for each trigger (event data stream) is1000. Upon arrival of a first level trigger, the data stream isstored in the multi-event memory. This memory has thecapacity to store either 4 events, if the event data stream islonger than 512 words, or 8 events otherwise. When thesecond level trigger (accept or reject) is received, the latestevent data stream is either frozen in the data memory until itscomplete readout takes place, or it is discarded. The completechain is contained in the Front-End Card (FEC) [4], eachcontaining 128 channels, which are located some 10cm awayfrom the pad plane and are connected to it by capton cables.In total the TPC is equipped with 4356 FECs grouped in 216readout partitions, with 6 partitions per TPC sector, eachcontrolled by a Readout Control Unit (RCU).As shown in figure 1, the RCU interfaces the FECs to theData Acquisition System (DAQ), the Timing and TriggerSystem (TTC) and the Detector Control System (DCS). TheRCU broadcasts the trigger information to the FECs, collectsthe trigger-related data from the FECs, assembles a sub-event,compresses the data and sends the compressed packed sub-event to the DAQ via optical fibre, the ALICE Detector DataLink (DDL) [5]. Moreover, the RCU has to initialise the FECsand monitor their behaviour reporting to the DCS anydetected fault.The radiation load on the TPC is low, with a total dosereceived over 10 years of less than 1Krad and a neutronfluency of less than 1011 n/cm2. Thus standard radiation-softtechnologies are suitable for the implementation of thiselectronics. However, some special care should be taken toprotect the system against potential damages caused by SingleEvent Effects (SEEs).II. RCU ARCHITECTUREThe RCU has the following functional requirements:I.  Distribution of the trigger and clock signals to the FECs.II. Initialisation of the FECs, including pedestal values,digital filter coefficients, zero suppression threshold, etc.III. Readout of trigger related data from the FECs, assemblyof a sub-event, compression of the data and transfer tothe DAQ via the ALICE Detector Data Link (DDL).IV. Supervision and monitoring the data flow and the statusof the FECs: power state, temperature, exception anderror conditions, etc.In this section we discuss each of the above functions and thecorresponding interfaces.A custom bus, the ALTRO bus [6], implements the maincommunication between the RCU and the FECs. The ALTRObus is essentially an extension of the FEC’s internal bus thatallows the RCU to access the FEC’s internal components. It isa multi-drop single-master bus where the RCU is the masterunit and the FECs are the slaves. In order to minimize thelength of the bus cables the RCU supports two branchesrunning in opposite directions. From the electrical point ofview the ALTRO bus is based on the GTL/GTL+ technology.All the RCU functions (I-IV) can be performed by means ofthe ALTRO bus. The ALTRO bus features a bandwidth of upto 200 Mbyte/sec. As shown in figure 1, an independentControl Network [7] establishes a dedicated bus connectionbetween the RCU and the FEC, in view of monitoring andcontrolling (function IV) the FECs without interfering withthe readout procedure. This Control Network is based on theI2C protocol, enhanced with an extra line for handlinginterrupts from the FECs, and supports a bandwidth of3.4Mbit/sec.Figure 1: Block diagram of the TPC readout partition. The RCUinterfaces a group of up to 25 FECs to the DAQ, the DCS and theTTC. The overall TPC readout consists of 216 readout partitions.The interfacing of the RCU to the Trigger and the DAQfollows the standard data-acquisition architecture of theALICE experiment [8]. The ALICE standard to transmit dataoff detector is the DDL technology (optical fibre). Itimplements a full duplex interface between the RCU and theRead Out Receiver Card (RORC), which is the first stage ofthe DAQ and is located in the experiment counting room. TheDDL provides the RCU with a bandwidth of 100Mbyte/sec inthe RCU→RORC direction and 10Mbyte/sec in theRORC→RCU direction. The DDL is composed of threehardware items: the Source Interface Unit (SIU), which isincorporated in the RCU, the fibre, and the DestinationInterface Unit (DIU), which is part of the RORC.  The SIU isa CMC-format mezzanine card plugged on the RCU as adaughter board.The RD12 TTC [9] system is the ALICE standard used todistribute trigger and clock information. Every RCUimplements an appropriate receiver (TTCrx), which producesthe phase-corrected LHC clock, Level-1 trigger and Level-2accept/reject. These are used on the RCU, and also distributedto all the FECs via the ALTRO bus. In addition, the TTCrxdelivers event identification information to be added to thesub-event header before sending the data to the DDL.For the communication between the RCU and the DCStwo technologies are under investigation: Profibus andEthernet.III. RCU CONTROL LOGICThe control logic of the RCU is divided into multiple statemachines (see figure 2). The Resource and Priority Manageris the master state machine, controlling all subsystems.Figure 2: Flowchart of the RCU control logic. The Resource andPriority Manager is the master state machine, controlling allsubsystems.A. ALTRO Controller Uses a custom protocol to service two ALTRO bus branchesand all ALTRO chips.  It builds and verifies ALTROcommands. The readout sequence of a TPC event is built upfrom information, stored in look-up tables, about the enabledand disabled channels. The amount of data received iscounted and cross-checked with the block length transferredby each individual ALTRO chip.B. SIU Controller.It transfers blocks of data form the RCU memory into theDDL SIU by means of the DDL protocol. Each block of datacontains one TPC sub-event. It also receives data from theDDL to be stored in the RCU memories or control registers.C. Trigger Manager (TTCrx).Manages the reception and distribution of triggers from theTTCrx chip. During the dead time of the TPC read out,incoming triggers are blocked. The TTCrx also suppliesinformation that will be included in the Data Header of eachsub-event. The Data Format of this header is an ALICEstandard described in [10]. The Trigger Manager includes alsothe logic to compare the number of triggers received by theRCU and by the ALTRO chips.D. RCU Resource & Priority Manager.The Resource & Priority Manager defines the priority of theincoming commands to the RCU. The standard operatingmode of the RCU is the readout of TPC data from theALTRO chips. The readout of one event is initiated by thereception of a Level-2 trigger from the TTCrx. The readout iscontrolled by the RCU. However, the data transfer from theALTRO to RCU cannot be split in pieces. Thus the memorymanager of the RCU must ensure that sufficient memory isavailable before starting a new data transfer. Wheneverneeded, the operator can ask to reconfigure either the RCU orthe ALTRO chips. A request is sent to the Resource &Priority Manager that executes the configuration only afterfinishing the ongoing readout. Incoming requests areexecuted, under the control of this state machine, during deadtime in readout.E. FEE Slow Control.Operates a dedicated bus connection between the RCU andthe Board Controller in each Front End Card (FEC). This isused for voltage and temperature probing, protocol and multi-event buffer errors reporting, and statistical data read out.F. Detector Slow Control.It accesses in write/read mode a set of RCU registersdedicated to store the values of the control/status parametersof the overall system (power state, temperature, errormessages, etc.). It connects the FEC’s Control to the DCSsystem.G. Huffman decoder (optional).Compression of data can be done on the RCU to makeeffective use of the available bandwidth and/or memory. Analgorithm for Huffman coding has been developed and tested[11, 12, 13].H. Watchdogs.Health agents, internal and external, that verify and monitorthe functionality of the RCU FPGA. SRAM based FPGAs arevulnerable to radiation SEU. If the watchdog reportsmalfunction, reconfiguration of the FPGA can be done byeither onboard or external configuration options.I. Debugging interface.PCI core for development and debugging.  Optional in thefinal version.The development of the RCU Control Logics is doneusing Mentor Tools (FPGA Advantage, ModelSim, Leonardo)and ALTERA Quartus II. Behavioural models (VHDL orVerilog) are used as test benches for the development of theinterface state machines.IV. RCU PROTOTYPEIn this section we describe two RCU prototypes that havebeen developed and tested with the rest of the TPC electronicscomponents.Figure 3: RCU Prototype I. This prototype is based on a comerciallyavailable PCI cards (PLDApplications) and a custom-mademezzanine card, which implements the interface to the FECs and theDDL SIU.A first prototype of the RCU (pRCU-I) has beendeveloped using the ALTERA EP20K400 FPGA on acommercial PCI-board (PLDA) [14]. The ALTRO protocol, amemory controller (FIFO structure) for accessing internal andexternal banks, and the SIU interface have been implementedin the FPGA and successfully tested. The set-up for the test ofthe complete readout chain is shown in figure 4.Figure 4:  Set-up for the test of the ALTRO electronics. The RCU-Iprototype is plugged in a PCI-slot of the PC on the left. One FEC isconnected to the RCU via the ALTRO bus prototype.A second prototype of the RCU has been developed and isbeing tested. The prototype is based on a PCI motherboardcarrying two mezzanine cards, an SIU board and a boardinterfacing the two FEC-busses, the TTCrx and the DCSsystem.  In this board all components required in the finaldesign are connected to the FPGA. The FPGA I/O-pins areconnected to 7 PMC connectors on which are plugged the twomezzanine cards.The external memory configuration is optimised to meetthe RCU requirements. Indeed, the memory is organised in 2banks with separate data and address lines.  This architectureallows the sub-event building of one event while transferringto the DAQ the previous event. The processing of the eventincludes adding a data header (including event length,identification and status) using the ALICE standard dataformat. Meanwhile, the sub-event stored in the other memorybank can be Huffmann-encoded (compressed) and pushed intothe DDL. Another use of this prototype is to test differenthardware options for the Detector Control System (DCS).Figure 5: RCU Prototype II layout. SRAM is organised in 2 bankswith separate data and address lines. The control logic is contained inthe onboard FPGA. The 7 PMC connectors are used to connect to theFPGA two mezzanine boards: the DDL SIU card and the FECinterface mezzanine card.  V. CONCLUSIONSThe RCU plays an important role in the readout andcontrol of the ALICE TPC front-end electronics. It interfacesthe front-end cards, which contain the complete readout chainto amplify, digitise process and buffer the detector signals, tothe DAQ, the Trigger and DCS. Besides the initialisation andreadout functionality the RCU provides features to diagnosticerrors and hardware faults.A first prototype of the RCU has been developed by usinga commercial PCI-board (PLDA), based on an EP20K400FPGA, and a custom PMC board. This first prototype (pRCU-I), which incorporates only the interface to the FECs and tothe DAQ, has been successfully used to validate the FEC andALTRO bus design. A second prototype (pRCU-II), based ona PCI motherboard carrying two mezzanine cards,incorporates all the RCU functions and will be tested with asignificant amount of the TPC electronics in the near future.   VI. REFERENCES[1] A Large Ion Collider Experiment, ALICE TPC  -Technical Design Report, December 1999, ISBN 92-9083-155-3, Geneva, Switzerland.[2] L. Musa et al., Front_End Electronics for the ALICE-TPCDetector, Proc. of the 4th  Workshop on Electronics for LHCExperiments, Rome, Sept. 21-25, 1998.[3] L. Musa et al., ALTRO User Manual, http://ep-ed-alice-tpc.web.cern.ch/ep-ed-alice-tpc/altro_chip.htm[4] R. Campagnolo et al., Front End Card,  http://ep-ed-alice-tpc.web.cern.ch/ep-ed-alice-tpc/fec.htm[5] G. Rubin, P. Vande Vyvre, ALICE Detector Data Link(DDL) – Interface Control Document, ALICE Internal Note,INT-96-43, December 1996.[6] L. Musa et al., The ALICE TPC Readout Bus, http://ep-ed-alice-tpc.web.cern.ch/ep-ed-alice-tpc/altro_bus.htm[7] B. Mota et al., The ALICE TPC Control Network,http://ep-ed-alice-tpc.web.cern.ch/ep-ed-alice-tpc/control_network.htm[8] CERN/LHCC 95-71 LHCC/P3, A Large Ion ColliderExperiment, ALICE-Technical proposal, Dec. 1995, ISBN 92-9083-077-8, Geneva, Switzerland.[9] TTC homepage: http://ttc.web.cern.ch/TTC/intro.html[10] P. Vande Vyvre et al., ALICE DAQ Data Format,http://edms.cern.ch/document/340186/[11] T. Jahnke, S. Schoessel and K. Sulimma, EDA group,Department of Computer Science, University of Frankfurt(2000).[12] J. Berger et al., TPC Data Compression, Nucl. Instrum.Meth. A489 (2002) 406-421.[13] A. Nicolaucig, M. Mattavelli, S. Carrato, Compression ofTPC data in the ALICE experiment, Nucl. Instrum. Meth. A,to be published in 2002.[14] PLDApplications, http://www.plda.com/hardw-pci20k.htm

Readout control unit of the front end electronics for the ALICE time projection chamber

Readout control unit of the front end electronics for the ALICE time projection chamber

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