Anelli, G

Anghinolfi, Francis

Campbell, M

Delmastro, M

Faccio, F

Florian, S

Heijne, Erik H M

Jarron, Pierre

Kloukinas, Kostas C

Marchioro, A

Rivetti, A

CERN Document Server

ANALOG DESIGN IN DEEP SUBMICRON CMOS PROCESSES FOR LHCA. Rivetti1,2, G. Anelli1, F. Anghinolfi1, M. Campbell1, M. Delmastro1,h, E. Heijne1, F. Faccio1,S. Florian3, P. Jarron1, K. Kloukinas1, A. Marchioro11 CERN, CH-1211 Geneve 23, Switzerland2Politecnico di Torino, Corso Duca degli Abruzzi 24, 10129 Torino, Italy3Università of Padova & INFN, via Marzolo 8, I-35131 Padova, Italy                                                          h Supported by Associazione per lo sviluppo scientifico e tecnologico del Piemonte (ASP)AbstractThe feasibility of analog integrated circuits for LHCexperiments in deep submicron CMOS technologies hasbeen investigated. This paper discusses general designissues and presents a systematic study of fundamentalanalog characteristics of commercial deep submicronCMOS processes.1.  INTRODUCTIONPresent state-of-the-art CMOS technologies integrateMOS transistors with a minimum gate length of 0.18 Pm-0.25 Pm and operate with a maximum power supply of2.5 V. The thin gate oxide used in these technologies hasa high tolerance to total dose effects. Therefore, circuitsdesigned in these technologies using dedicated layouttechniques (enclosed layout transistors and guard-rings)show a total dose resistance complying LHCspecifications [1].Some of the integrated circuits for LHC have moreoverstrict requirement on integration and low powerconsumption, especially in the inner parts of thedetectors. A deep submicron technology is therefore avery suitable choice for digital ASIC design, whereas itsuse for analog and mixed-mode circuits must beinvestigated more carefully.Commercial submicron technologies are in fact mainlyintended for large volume digital applications. The dataavailable from the manufacturers concerning propertieslike noise and matching may be not completelysatisfactory from the analog designer’s point of view. Thepower supply allowed by a typical 0.25 Pm technology(2.5 V) is almost at the edge of the use of standard analogdesign techniques. This is of particular concern, forinstance, for circuits like switched capacitors analogmemories, which are extensively used in high energyphysics applications.A submicron technology offers however attractivefeatures also to the analog designer. The many layers ofinterconnects can be used to improve the quality ofanalog signals, especially in mixed-mode designs. Due tothe squeezed design rules, also density can improve,though not in the same proportion as for digital circuits.The aim of this work is to investigate the analogperformances of commercial 0.25 Pm CMOStechnologies.In section 2 we discuss the main design aspects whichhave to be considered in using a deep submicrontechnology for analog and mixed-mode design. Section 3describes the test structures we have designed toinvestigate the analog performances of the technologiesand in section 4 measurements performed on suchstructures are presented.2.  DESIGN ISSUES2.1 NoiseThe input-referred spectral density of the channelthermal noise can be expressed as [2] g1 1kT4Vm2n JG (1).In the above equation k is the Boltzmann constant and Tis the absolute temperature.For an ideal device, J = 2/3* in strong inversion andJ  = 1/2* in weak inversion. * is the so called excessnoise factor and indicates how much the measured noiseexceeds the theoretical value calculated using the longchannel MOS equations. Values of * reported in theliterature for non submicron technologies range from 1 to1.5 [3].The correction term (1 + G) is introduced to take intoaccount the effect of fixed bulk charge on gm [2,4].The transconductance gm in strong inversion is definedby the well known equationI)L/W(K2g DSm  (2).Due to the thin gate oxide, the parameter K=PCoximproves in submicron technologies, as can be seen fromtable 1.Table 1: Technological parameter for different CMOStechnologies (NMOS).Lmin (Pm) tox (nm) K (PA/V2)1.2 24 680.8 14 900.5 10 1340.25 5 280For instance, a transistor with W=20 Pm, L=2 Pm, andIDS=100 PA will have a gm of about 370 PS ifimplemented in a 1.2 Pm technology and of 780 PS ifproduced using a 0.25 Pm technology.In a deep submicron process, however, the possibilityof scaling the L of the transistors is not as useful as itcould be argued form eq. (3). In fact, for short channeldevices, the increase in transconductance predicted by (3)is limited by velocity saturation effects [4]. Additionaleffects like hot carriers and weak avalanche phenomenamay also worsen the noise performances, increasing *significantly above 1 [4].The increase in K has anyway an interesting effect,because it increases also the current limit between weakand strong inversion. This current is defined as [5]U)L/W(nK2I 2Tlim  (4)where n is the slope factor and UT is the thermal voltage.This limit for a fixed aspect ratio is a linear function ofK. In other words deep submicron makes weak inversionoperation easier. This is an attractive feature for low noiseand low power amplifiers, since the weak inversionoperation maximises the transconductance to current ratioand minimises the input referred noise for a given powerbudget.The other source of noise which has to be considered isthe flicker noise. The flicker noise spectral density can beexpressed as [3]f1WLCKV 2oxa2n D (5).Due to the increase in Cox the flicker noise for a giventransistor area is expected to reduce if the device isimplemented in a submicron technology [6].2.2 MatchingThe matching between nominally identical componentsplays an important role in basic analog building blockslike differential amplifiers, comparators and currentmirrors.The threshold voltage mismatch of MOS transistors ischaracterised by measuring the difference between thethresholds of many couples of nominally identicaldevices. The standard deviation of the differencedistribution is usually used as a measure of mismatch andis described by the following equationWLAVthVth  V (6).The term AVth is a constant for a given technology andis given byoxVth tBA  (7)where tox is the oxide thickness and B can be assumed tobe 1 mVPm/nm for many different processes [7].Data available in literature clearly indicate that AVthreduces with the oxide thickness [8,9]. A submicrontechnology has therefore better threshold matchingperformances for a given transistor area.The standard deviation in case of the current gainfactors E=K(W/L) is expressed asWLA/EEEV  ' (8).Values of AE found in literature are 1-3 %Pm [10].However, in high energy physics applications encloseddevices are often required to guarantee an adequateradiation resistance. Results about matching properties ofenclosed transistor are described in section 4.2.3 Power supply limitationsA 0.25 Pm CMOS technology typically operates withpower supply of 2.5 V. Transistor threshold voltages arein the order of 450-550 mV. The maximum signal swingis hence reduced compared to a 5 V technology, and canconsequently affect the dynamic range.The most serious drawback of the required low voltageoperation may occur in switched capacitor circuits. Theelementary sampling cell of fig. 1 is used as an example.Fig. 1: CMOS transmission gate.Let’s suppose that the switch is closed (ck = Vdd, ck_b= 0). In principle, in these conditions, the switch shouldprovide a low impedance path and any voltage between 0and Vdd could be sampled on capacitor Cs.However, it can be shown that if Vdd is smaller than thesum of the threshold voltages of the two transistors, aregion exists in which neither device conducts. Therefore,when the switch is closed a low impedance path for eachvalue of Vin between 0 and Vdd is not guaranteedanymore. This, of course, affects very seriously thedynamic range of conventional switched capacitorcircuits.In evaluating the minimum power supply required bythe circuit of fig. 1 to work properly care must be paid tothe bulk effect, which can rise the threshold voltages upto 1 Volt [6].The minimum voltage is therefore about 2 V, which isnot very far from the maximum operating voltage of aquarter micron technology (2.5 V).On the other hand, in switching circuits powerconsumption benefits a lot from the reduced supply. Acapacitive ladder of a charge redistribution A/D converteroperating at 2.5 V will dissipate only 25% of the powerrequired by a converter operating at 5 V (provided, ofcourse, that capacitor size and operating frequencyremain the same) [5].2.4 Digital noise couplingThe front end chip used in high energy physicsapplications are mixed mode circuits in which sensitiveanalog parts (low noise preamplifiers) are implementedon the same chip together with digital functions. In somecases, the amount of digital logic required can be veryhigh.In submicron technologies the devices are usually builtin a relatively thin (few microns) high resistivity layerwhich is epitaxially grown on a highly conductive bulk.This bulk provides a medium by which the switchingnoise of the digital part can easily propagate to the analogcircuitry.The best way to overcome this problem is to physicallyglue the backside of the chip to a ground plane. Thissolution is not always practical, because the backside isoften passivated and a thinning-metallization procedurewould be required.Actually, it is worth saying that this problem is notpeculiar to deep submicron technologies only. A largefraction of the mixed mode technologies currentlyavailable are derived from former pure digital processesand use the low doped epitaxial layer grown on a highlyconductive wafer.Deep submicron technologies offer however a highnumber (5 to 7) of metal layers for the interconnections.These layers can be used to avoid any sharing of powerand grounding paths between digital and analog circuits.3  TEST STRUCTURESTo study the problems discussed above a number oftest structures were designed in 0.25 Pm CMOStechnology, namely:x transistor pairs for matching measurements;x wide transistors for noise measurements;x transimpedance amplifiers;x an analog memory and a switched capacitorsuccessive approximation A/D converter.The noise structures and the transimpedance amplifierswere implemented in two different technologies, whereasthe other structures were designed only for onetechnology.Up to now it has been possible to measure widetransistors (in both technologies, hereafter referred to astech_a and tech_b), matching structures and the amplifierimplemented in tech_a.The results of these tests are discussed in the followingsection.4.  TEST RESULTS4.1 Noise measurementsThe noise measurements have been carried out for alldevices in the three different regions of operation. Theappropriate bias current for each device has been selectedthrough a measurement of the gm/Id characteristic.A typical gm/Id curve is shown in figure 2.0510152025301.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01ID [A]gm/I D [S/A]Figure 2: Typical gm/Id curve.For our measurements, we have chosen the followingcurrents:x 30 PA for weak inversionx 500 PA for moderate inversionx 20 mA for strong inversionIn figure 3 and 4 typical noise spectra for NMOS andPMOS transistors are shown for both technologies. Thesespectra were obtained biasing the transistors in themoderate inversion region, with a current of 500 PA andapplying a drain-source voltage of 800 mV.From the measurements we have estimated the excessnoise factor * and the flicker noise coefficient Ka. Theexcess noise factors are reported in table 2.We point out that for the moderate inversion region wehave reported J, since in this region the value of theinversion layer thermal noise coefficient (which is 2/3 instrong inversion and 1/2 in weak inversion) is not exactlyknown.In weak and moderate inversion the excess noise factoris comparable to what is found in literature for nonsubmicron technologies [2,3].1.0E-091.0E-081.0E-071.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08frequency (Hz)input noise (V/sqrt(Hz))NMOS PMOSFigure 3: Example of noise spectra for devices of tech_a(Ibias=500 PA: moderate inversion) W/L=1000/0.35.1.0E-091.0E-081.0E-071.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08frequency (Hz)input noiseNMOS PMOSFigure 4: Example of noise spectra for devices of tech_b(Ibias=500 PA: moderate inversion) W/L=2000/0.78.Table 2: Excess white noise factors.tech_a tech_bW.I. * = 1.1 * = 1.1M.I. J = 0.85 J = 0.65S.I.   * < 5.5   * < 3.4The higher values of * we have found in strong inversionare consistent with other results previously reported forsubmicron technologies [4].However, it is worth pointing out that a typical inputtransistor of a low noise front-end amplifier (W/L from200/1 to 2000/1 and bias current from 50 PA to 500 PA)would rather operate in weak or moderate inversion.The highest value of the flicker noise coefficient Ka wehave measured for PMOS transistors is 610-28 C2/m2. ForNMOS transistors the maximum value is 310-27 C2/m2.A value which is used in noise calculations for NMOStransistors in conventional technologies is 610-27 C2/m2[3], which is in the same order of magnitude.4.2 Matching measurementsIn this work we have investigated in particular thematching behaviour of enclosed devices.We have measured about 100 chips. Each chip contains 5enclosed NMOS differential pairs with different gatearea. For each device we have extracted the thresholdvoltage, the E and the standard deviations of thedifference distribution have been calculated.We have observed that enclosed devices followequation (6) and (8) for small gate areas, whereas theyexibit a “saturation” behaviour for gate area above50 Pm2.We have therefore modified equations (6) and (8) asfollowingVV 0Vth2Vth2VthWLA¸¸¹·¨¨©§ (10)andVV EEEE 022/WLA¸¸¹·¨¨©§ ' (11).The value found for AVth is 5.4 mV/Pm which isconsistent with eq. (7) since tox is about 5.5 nm in thistechnology. The value of VVth0 is 0.95 mV. For AE wefound a value of 1.5% Pm, with VE0=0.33%.Due to these “saturation effects”, enclosed layouttransistors tend to have worse matching performances.The values at which the saturation occurs are howeverstill compatible with the needs of precise analog design.4.3 Transimpedance amplifier resultsThe transimpedance amplifier uses the scheme detailedin [11,12] in which a current controlled gm stage in usedas feedback around a single stage cascode amplifier. Theinput device of the preamplifier is a NMOS withW/L=500/0.35; an oxide capacitance per unit area of6.9 fF/Pm2 and a gm of 7 mS for the input transistor havebeen used in the noise calculations. The transimpedancegain has been adjusted to 300 k:. In the test set-up, thecapacitance seen by the input of the preamplifier wascalculated to be 5 pF.The output measured with a digital oscilloscope inthese conditions is reported in fig. 5.Figure 5: Preamplifier pulse response (input charge:4 fC).The output swing for 4 fC input signal is 37.5 mV,with a peaking time of 13 ns. The output noise wasmeasured with a true r.m.s voltmeter and was found to beabout 0.7 mV r.m.s, which corresponds to an inputreferred noise of 434 electrons. The noise slope was81 electrons/pF. This value agrees with the one calculatedfor a second order system (72 electrons/pF) using theformulae proposed in [3].5  CONCLUSIONSIn this work basic issues related to the use of deepsubmicron technologies for analog integrated circuitsdesign have been investigated and dedicated teststructures have been designed.Particular care has been paid to the study of the noiseperformances of the technologies and of the matchingproperties of enclosed layout devices, which are neededin most applications in order to achieve the requiredradiation resistance.The results on the matching of enclosed transistorsshow that the dispersion of the threshold voltage saturatesat a value of 0.95 mV for transistor area above 50 Pm2.This, however, is not a serious drawback for most analogapplications.The noise excess factors found in weak and moderateinversion are close to the minimum theoretical values.Higher excess noise factor have been measured in stronginversion. This region of operation should be avoided ininput transistors of low noise amplifiers.A transimpedance amplifier has been completelycharacterised. For a power consumption of 1 mW, theamplifier gain is 9.4 mV/fC and the input referred noisefor an input capacitance of 5 pF is 434 electrons r.m.s.The noise slope (80 electrons/pF) is consistent with thetheoretical calculations (gm of the input transistor 7 mS)for a second order system, given the short peaking time(13 ns).Test performed up to now show the compatibility ofthe measured devices with the requirements of low noiseand precise analog designs. Some penalty can be paid ifenclosed layout transistors are used in structures whoseperformances heavily rely on matching.6  REFERENCES[1] M. Campbell et al., "A pixel readout chip for 10-30Mrad in standard 0.25 Pm CMOS", IEEETransactions on Nuclear Science, vol. 46, pp. 156-160, June 1999.[2] S. Tedja, H.H Williams, J. Van der Spiegel, F.M.Newcomer, and R. Van Berg, “Noise spectral densitymeasurements of a radiation hardened CMOS processin the weak and moderate inversion”, IEEETransactions on Nuclear Science, vol. 39, no. 4, pp.804-808, 1992.[3] Z.Y. Chang and W.M.C. Sansen, "Low-noise wide-band amplifiers in bipolar and CMOS technologies",Kluwer Academic Publishers, 1991.[4] Y. Tsividis, “Operation and modeling of the MOStransistor”, McGraw-Hill, 1999.[5] F.Maloberti, F. Francesconi, P. Malcovati andO.J.A.P. Nys, “Design consideration on low-voltagelow-power data converter”, IEEE Transactions onCircuits and Systems-I: Fundamental theory andapplications, vol. 42, no. 11, pp. 853-863, 1995.[6] W. Sansen, “Low-voltage Low-power analog CMOSdesign”, Course at the Ecole Polytechnique Fédéralede Lausanne, Lausanne, Switzerland, June 1999.[7] M.J.M. Pelgrom, H.P. Tuinhout and M. Vertregt,"Transistor matching in analog CMOS applications",Technical Digest of the International ElectronDevices Meeting 1998, San Francisco, California,USA, 6-9 December 1998, pp. 915-918.[8] M.J.M. Pelgrom and M. Vertregt, “CMOStechnology for mixed signal Ics”, Solid-StateElectronics, vol. 41, no. 7, pp. 967-974, 1997.[9] T. Mizuno, J. Okamura, and A. Toriumi,“Experimental study of threshold voltage fluctuationdue to statistical variation of channel dopant numberin mosfet’s” IEEE Transactions on Electron Devices,ED-41, pp. 2216-2221, 1994.[10]`H.P. Tuinhout, "Matching of MOS Transistors",Course at the Ecole Polytechnique Fédérale deLausanne, Lausanne, Switzerland, 12-15 October1998.[11]F. Anghinolfi et al. “A transimpedance amplifierusing a novel current mode feedback loop”, CERN,ECP/95-10, 1995.[12]G. Cervelli, R. Grabit, P. Jarron, A. Rivetti,G. Stefanini, F. Vasey, “A low noise CMOSpreamplifier for analog electro-optical fibre links”,CERN/LHCC/96-39, 1996.

Analog design in deep submicron CMOS processes for LHC

Analog design in deep submicron CMOS processes for LHC

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