Microprogrammed Digital Signal Processors (DSP) are frequently used as a solution to embedded processor applications. These processors utilize a control memory which permits execution of the processor\u27s instruction set architecture (ISA). The control memory can take the form of a static, read only memory (ROM) or a dynamic, writeable control memory (WCM), or both. Microcoding the WCM permits redefining the processor\u27s ISA and provides speedup due to its instruction level parallelism (ILP) potential. In the past, code generation efforts for microprogrammable processors focused on creating assembly and microcode as two separate steps. In this thesis an alternative approach was chosen which combines the separate code generation steps into one automated, dual-target compilation process using the advanced techniques of VLIW compiler technology. The architecture chosen for this effort is a microprogrammable DSP being developed by Rome Labs, New York. The prototype compiler developed in this effort has demonstrated the potential for speedup of microcoded program portions over their assembly code counterparts. Therefore, the feasibility of program speedup produced by a dual-target compiler using VLIW compilation techniques has been validated
