Formats for representing and manipulating verification problems are extremely
important for supporting the ecosystem of tools, developers, and practitioners.
A good format allows representing many different types of problems, has a
strong toolchain for manipulating and translating problems, and can grow with
the community. In the world of hardware verification, and, specifically, the
Hardware Model Checking Competition (HWMCC), the Btor2 format has emerged as
the dominating format. It is supported by Btor2Tools, verification tools, and
Verilog design tools like Yosys. In this paper, we present an alternative
format and toolchain, called Btor2MLIR, based on the recent MLIR framework. The
advantage of Btor2MLIR is in reusing existing components from a mature compiler
infrastructure, including parsers, text and binary formats, converters to a
variety of intermediate representations, and executable semantics of LLVM. We
hope that the format and our tooling will lead to rapid prototyping of
verification and related tools for hardware verification.Comment: Formal Methods in Computer-Aided Design 202