The NEORV32 RISC-V Processor

Abstract

<h2>What's Changed</h2> <ul> <li>Update software framework to gcc-13.2.0 by @stnolting in https://github.com/stnolting/neorv32/pull/705</li> <li>[cpu] minor cleanups and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/707</li> <li>⚠️ remove Zifencei generic - Zifencei ISA extension is now always enabled by @stnolting in https://github.com/stnolting/neorv32/pull/709</li> <li>[sw/lib] add nerov32-flavored vprintf funtion by @stnolting in https://github.com/stnolting/neorv32/pull/711</li> <li>[sim] Add GHDL run flags variable by @stnolting in https://github.com/stnolting/neorv32/pull/715</li> <li>Move FreeRTOS port & demo into new repository by @stnolting in https://github.com/stnolting/neorv32/pull/716</li> <li>Fix bug in neorv32_slink_available() function by @Unike267 in https://github.com/stnolting/neorv32/pull/717</li> <li>[rtl] cleanups and code beautification by @stnolting in https://github.com/stnolting/neorv32/pull/718</li> <li>[sw] update crt0's early-boot trap handler by @stnolting in https://github.com/stnolting/neorv32/pull/719</li> <li>[rtl] upgrade neoTRNG to version 3 by @stnolting in https://github.com/stnolting/neorv32/pull/721</li> <li>Fix-up the litex wrapper by @Unike267 in https://github.com/stnolting/neorv32/pull/722</li> <li>minor rtl code cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/723</li> <li> provide full hardware reset for all FFs by @stnolting in https://github.com/stnolting/neorv32/pull/724</li> </ul> <h2>New Contributors</h2> <ul> <li>@Unike267 made their first contribution in https://github.com/stnolting/neorv32/pull/717</li> </ul> <p><strong>Full Changelog</strong>: https://github.com/stnolting/neorv32/compare/v1.9.0...v1.9.1</p>If you are using this project, please cite it as below

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