Dynamically scheduled high-level synthesis (HLS) achieves higher throughput
than static HLS for codes with unpredictable memory accesses and control flow.
However, excessive dataflow scheduling results in circuits that use more
resources and have a slower critical path, even when only a part of the circuit
exhibits dynamic behavior. Recent work has shown that marking parts of a
dataflow circuit for static scheduling can save resources and improve
performance (hybrid scheduling), but the dynamic part of the circuit still
bottlenecks the critical path. We propose instead to selectively introduce
dynamic scheduling into static HLS. This paper presents an algorithm for
identifying code regions amenable to dynamic scheduling and shows a methodology
for introducing dynamically scheduled basic blocks, loops, and memory
operations into static HLS. Our algorithm is informed by modulo-scheduling and
can be integrated into any modulo-scheduled HLS tool. On a set of ten
benchmarks, we show that our approach achieves on average an up to 3.7×
and 3× speedup against dynamic and hybrid scheduling, respectively, with
an area overhead of 1.3× and frequency degradation of 0.74× when
compared to static HLS.Comment: To appear in the 33rd International Conference on Field-Programmable
Logic and Applications (2023