Minimizing Sensitivity to Clock Skew Variations Using Level Sensitive Latches

Abstract

We propose a method for improving the tolerance of synchronous circuits to delay variations on the clock distribution. Instead of retiming and clock skew scheduling applied to edge-triggered flip-flops, as used by most other methods, we use level-sensitive latches placed based on a schedule of the operations. The resulting circuit can have a non-zero tolerance even at the optimal clock period, which is impossible with edge-triggered flip-flops