In recent years, static power side-channel analysis attacks have emerged as a
serious threat to cryptographic implementations, overcoming state-of-the-art
countermeasures against side-channel attacks. The continued down-scaling of
semiconductor process technology, which results in an increase of the relative
weight of static power in the total power budget of circuits, will only improve
the viability of static power side-channel analysis attacks. Yet, despite the
threat posed, limited work has been invested into mitigating this class of
attack. In this work we address this gap. We observe that static power
side-channel analysis relies on stopping the target circuit's clock over a
prolonged period, during which the circuit holds secret information in its
registers. We propose Borrowed Time, a countermeasure that hinders an
attacker's ability to leverage such clock control. Borrowed Time detects a
stopped clock and triggers a reset that wipes any registers containing
sensitive intermediates, whose leakages would otherwise be exploitable. We
demonstrate the effectiveness of our countermeasure by performing practical
Correlation Power Analysis attacks under optimal conditions against an AES
implementation on an FPGA target with and without our countermeasure in place.
In the unprotected case, we can recover the entire secret key using traces from
1,500 encryptions. Under the same conditions, the protected implementation
successfully prevents key recovery even with traces from 1,000,000 encryptions