Large language models (LLMs) have garnered significant attention across
various research disciplines, including the wireless communication community.
There have been several heated discussions on the intersection of LLMs and
wireless technologies. While recent studies have demonstrated the ability of
LLMs to generate hardware description language (HDL) code for simple
computation tasks, developing wireless prototypes and products via HDL poses
far greater challenges because of the more complex computation tasks involved.
In this paper, we aim to address this challenge by investigating the role of
LLMs in FPGA-based hardware development for advanced wireless signal
processing. We begin by exploring LLM-assisted code refactoring, reuse, and
validation, using an open-source software-defined radio (SDR) project as a case
study. Through the case study, we find that an LLM assistant can potentially
yield substantial productivity gains for researchers and developers. We then
examine the feasibility of using LLMs to generate HDL code for advanced
wireless signal processing, using the Fast Fourier Transform (FFT) algorithm as
an example. This task presents two unique challenges: the scheduling of
subtasks within the overall task and the multi-step thinking required to solve
certain arithmetic problem within the task. To address these challenges, we
employ in-context learning (ICL) and Chain-of-Thought (CoT) prompting
techniques, culminating in the successful generation of a 64-point Verilog FFT
module. Our results demonstrate the potential of LLMs for generalization and
imitation, affirming their usefulness in writing HDL code for wireless
communication systems. Overall, this work contributes to understanding the role
of LLMs in wireless communication and motivates further exploration of their
capabilities