Altmeyer, S.

Sapra, D.

English

In this paper we outline Design Space Exploration methodology aimed at homogeneous multi-core architectures, where the safety-criticality is the crux of a system design. Multi-core architectures provide better computational abilities, but at the same time complicate the computation of timing bounds. Determining suitable architectures that achieve timing requirements is an important aspect for a system designer. The proposed work conceptualizes ways to automate and explore different design facets of a multi-core processor. The intention is to ensure that the particular application meets its deadlines, while optimizing other objectives such as minimizing hardware costs, energy consumption and floor area. The automated exploration builds upon Mulitcore Response Time Analysis for timing verification and multicube for heuristic search methods. The aim is to generate an architecture design in the end that can be used directly to build a custom application specific processor

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UvA-DARE is a service provided by the library of the University of Amsterdam (https://dare.uva.nl)UvA-DARE (Digital Academic Repository)Work In Progress: Design-Space Exploration of Multi-core Processors forSafety-Critical Real-Time SystemsSapra, D.; Altmeyer, S.DOI10.1109/RTSS.2017.00040Publication date2017Document VersionAuthor accepted manuscriptPublished in2017 IEEE Real-Time Systems SymposiumLink to publicationCitation for published version (APA):Sapra, D., & Altmeyer, S. (2017). Work In Progress: Design-Space Exploration of Multi-coreProcessors for Safety-Critical Real-Time Systems. In 2017 IEEE Real-Time SystemsSymposium: proceedings : 5-8 December 2017, Paris, France (pp. 360-362). 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Youwill be contacted as soon as possible.Download date:09 Mar 2023Work In Progress: Design-Space Exploration ofMulti-core Processors for Safety-Critical Real-Time SystemsDolly SapraUniversity Of AmsterdamD.Sapra@uva.nlSebastian AltmeyerUniversity Of Amsterdamaltmeyer@uva.nlAbstract— In this paper we outline Design Space Explorationmethodology aimed at homogeneous multi-core architectures,where the safety-criticality is the crux of a system design.Multi-core architectures provide better computational abilities,but at the same time complicate the computation of timingbounds. Determining suitable architectures that achieve timingrequirements is an important aspect for a system designer.The proposed work conceptualizes ways to automate andexplore different design facets of a multi-core processor. Theintention is to ensure that the particular application meets itsdeadlines, while optimizing other objectives such as minimiz-ing hardware costs, energy consumption and floor area. Theautomated exploration builds upon Mulitcore Response TimeAnalysis for timing verification and multicube for heuristicsearch methods. The aim is to generate an architecture design inthe end that can be used directly to build a custom applicationspecific processor.I. INTRODUCTIONWith the increasing computational demand of futureembedded systems, single-core processors will be replaced bymodern, often application-specific multi-core designs. Multi-cores provide better performance/power ratio as well asmore freedom to architect an application-specific embeddedsystem. The assemblage of types of cores, number of cores,memory system, bus policy etc. allow the system designer toselect an architecture which satisfies a range of application’sdesign objectives. A design objective of real-time embeddedsystems, such as automotive or aerospace systems, is timingcorrectness, typically expressed via deadline requirements. Incase of safety-critical systems, these requirements are strict,which means that the system do not serve its purpose if atask in the application fails to complete before its deadline.The large design-space combined with the stringent timingrequirements, poses a significant challenge to the designerof safety-critical multi-core systems: finding an application-specific multi-core design which fulfils all timing require-ments, while optimizing all other design objectives, suchas for instance minimizing power consumption, hardwarecosts, etc. In this paper, we sketch a design-space explorationfor safety-critical real-time multi-core systems. We combinedesign-space exploration (DSE) techniques – well knownalready within the realm of multimedia applications – usinggenetic algorithms, with novel timing analysis techniques.Ultimately, we aim to automatically create a multi-corearchitecture design, following the result of the DSE, that candirectly be used to build a prototype FPGA processor. Such acustomized application-specific processor (that ensures timingcorrectness of safety-critical applications) can help build aquick prototype to be used in later design stages, or evenserve as an end product for low volume systems.II. MULTI-CORE TIMING VERIFICATIONWe assume an application consisting of a number of tasks,which realize different functionalities of the system. Timinganalysis derives bounds on execution times, i.e., worst-caseexecution times (WCET) for each task. On a single core,timing bounds can be achieved through analysing executiontimes of tasks in isolation along with the processor schedulingpolicy. The WCETs of all tasks are then fed to a schedulabilityanalysis, which computes each task’s worst-case responsetime (WCRT), i.e., the worst-case delay between task releaseand task completion. If a task’s WCRT is less than or equalto its deadline, the task is deemed schedulable. A task set isdeemed schedulable if every task is deemed schedulable.In a multicore system however, timing analysis is morecomplicated as there can be cross-core interference fromshared hardware resources such as memory subsystems andcommon interconnects. Deriving WCETs in isolation, ascommonly done for single-core system, will lead to eitherimprecise or optimistic execution time bounds.Recently, a novel timing verification approach [1] formulticore systems has been developed, which combinesthe WCET and WCRT analysis in one framework, calledthe Multicore Response Time Analysis (MRTA). The MRTAframework dissects the effects of the individual componentsof a multicore system (processor and memory demands) thatcontribute to the execution-time and re-assembles them at thelevel of the worst-case response time analysis. The analysisconsiders the worst-case behaviour of hardware resources,such as the memory bus, over long durations equating totask response times, rather than summing the worst case overshort durations, such as single bus accesses. We build theDSE framework by extending this MRTA framework.We represent an application with a set of n sporadic tasks{τ1, . . . ,τn}, each task τi has a minimum period or inter-arrival time Ti and a deadline Di. Deadlines are assumedto be constrained, hence Di ≤ Ti. The execution of task τiis modelled using a set of traces Oi , where each traceis an ordered list of instructions. Each instruction carriesinformation about the memory locations accessed (if any).We assume that the tasks are independent, i.e., they do notshare mutually exclusive software resources, however, taskscompete for hardware resources such as the processor, mem-ory, and the bus. The index of each task is unique and thusprovides a global priority order, with τ1 having the highestpriority and τn the lowest. A subset of the tasks is assignedto each core, with local priority ordering. Furthermore, tasksfollow fixed-priority preemptive scheduling.In MRTA, the response time Ri of task τi on core Px isgiven by the following recurrence relation:Ri = PDi + IPROC(i,x,Ri)+ IBUS(i,x,Ri)+ IDRAM(i,x,Ri) (1)where PDi is the processor demand, which equates to theexecution time of task τi in isolation assuming a perfect busand memory with zero latency. IPROC is the interferenceon the core due to higher priority tasks preempting ordelaying task τi. IBUS is the interference on the bus computedusing a mathematical model of the bus arbiter. IDRAM isthe interference due to DRAM refreshes. The processordemand PD, but also the memory demand MD, whichdenotes the number of bus accesses of a task and feeds intothe computation of the IBUS and IDRAM, are computed byanalysing the task’s execution traces. The iterations start withthe no-interference response time and completes either whena task’s response time bound exceed the task’s deadline, orwhen each task’s response-time bound reaches a fixed-pointless than or equal to the task’s deadline, in which case the taskset is deemed schedulable. We use this analysis to determineif a task set is schedulable on the given architecture.The MRTA framework represents a generic and compo-sitional solution for response time analysis. It is flexible inthat it can be instantiated with various architecture designselections. It can model variable number of cores, withdifferent arbitration policies, as well as multifarious memorymodels (uncached systems, data and instruction caches,scratchpads, etc., and any combination of them). We referto [1] and [2] for details on the MRTA framework.III. DESIGN-SPACE EXPLORATION OFSAFETY-CRITICAL EMBEDDED SYSTEMSIn any embedded system, ensuring that all design objectivesare met is not trivial. We can think of design space as a unionof parameters and objective space (See Figure 1). Parametersare the available design choices and due to a number ofpossible parameter combinations, the parameter space canbe exponentially large. The values of the objective spaceneed to be acquired from relevant evaluation mechanisms,which in real-life design can not usually be trivially derivedin reasonable time.Fig. 1. Design space broken down into parameter and objective space.(taken from [3])Most of the times, the true optimum is hard to find becausethere simply might not be a solution where all objectivesare simultaneously met. This problem is compounded by thefact that the parameter space is too large to allow for ananalysis of each point in the parameter space. For this reason,finding a design point that meets design requirements as bestas possible is often considered sufficient.Evaluating a single design point can take a considerableamount of time. Therefore, an efficient DSE should be ableto use each evaluation result to either reject unsuitable partsof the design space or determine the direction of traversal insubsequent iterations. The aim is to minimize total number ofevaluations needed to find a good solution (which might notbe the best solution – a trade-off between time and accuracy).DSE frameworks typically starts with a randomly chosendesign point to evaluate and with each iteration attemptsto move towards the optima. There are numerous heuristicalgorithms available, like genetic algorithm, particle swarmoptimization, simulated annealing and ant colony optimization,that govern the design space traversal by utilizing theevaluation result as feedback.A. Application modelA given application is the starting point for this DesignSpace Exploration. We build our application model on theMRTA’s task model, which in turn uses traces containingmemory access information for each instruction. The memoryinformation is needed to evaluate interferences based onmemory demands on local memory as well as bus demandsfor main global memory and traces represent that informationwithout overly complicating the analysis.Initially we propose to use Mälardalen benchmark suite [4]to provide traces and later we aim to get traces from a realtime application. The benchmarks have been compiled to theARMv7-architecture, which also serves as the initial selectionfor our DSE framework.B. Parameter SpaceIn our context, we model a generic homogeneous mul-ticore architecture. Such a platform consists of l timing-compositional cores P1, . . . ,Pl as depicted in Figure 2. Bytiming-compositional cores we mean cores where it is safeto separately account for delays from different sources, suchas computation on a given core and interference on a sharedbus [5]. We assume homogenous cores, each with a localmemory connected via a shared bus to a global memoryand IO interface. We assume constant delays to retrieve datafrom global memory under the assumption of an immediatebus access. Bus transactions are atomic, which are not re-ordered, and non-preemptable busy waiting on the processorfor requests to be serviced. Further, we assume that bus accessmay be given to cores for one access at a time.Fig. 2. Typical Multi-core platform with l cores with local memories,connected via a shared bus to the global memory.In such a general multicore system, design parameters thatcan be varied and used for evaluation are• Number of cores• Local memory types - cache, partitioned cache andscratchpads• Local memory, data and instruction, cache sizes• Global memory delays• Bus arbitration policy• Task to core mappingThese parameters have different types of justifiable valuesand they need to be appropriately defined for the exploration.For example, memories can have fixed ranges, i.e. minimumand maximum allowed values which also have power oftwo progression. Bus arbitration policy is chosen from oneof possible type like FIFO, Fixed Priority etc. The MRTAframework, which we use to evaluate individual design pointsis able to handle any combination of these paramters.C. Evaluation StrategyFor an efficient exploration, we need fast and accurateevaluation mechanism for all objectives. Timing correctnesscomes from MRTA, which tells us if the application isschedulable or unschedulable after the analysis. Along withschedulability we need to evaluate the overall hardware costand the floor area on an FPGA.To have a single module that performs all evaluations, wehave created a wrapper around MRTA, which accepts anarchitecture file, evaluates time bounds and then using simplemetrics calculates the hardware cost. In future we aim to findsuitable FPGA for floor plan evaluations as well as to generatean appropriate design file in the end. In exploration automatedtools, objectives are also called system metrics. The tool isinstantiated with configurable settings to optimize (maximizeor minimize) a system metric over multiple iterations. Tofasten up evaluation, we reuse partial evaluations in differentiterations wherever possible and do not calculate other systemmetrics when a task is deemed unschedulable.D. DSE MethodologyIncorporating all the ideas presented above, we build thewhole framework as depicted in Figure 3. A full search withevaluation of each and every single point in the design spaceis prohibitively slow due to the size of the design space andsince the analysis may take several minutes to validate theschedulability on a mutlicore design. The number of designpoints that can be realistically evaluated is hence limited.We use heuristic search techniques that can be used tosearch the design space using a subset of design pointevaluations for an optimal solution. A good search techniqueshould be able to take feedback from evaluation results andmodify its search methodology accordingly. A few automatedDSE frameworks already exist, for example, Multicube [6]and FADSE [7], that can be utilised to explore the designspace based on various heuristics like genetic algorithms,particle swarm optimization and simulated annealing.We have two modules in the proposed approach – anautomated design-space exploration module and an evaluationFig. 3. Experimental design-space exploration setupmodule. They communicate back and forth using predefinedcommunication protocol. MRTA framework is used insidethe wrapper module that also analyses other system metrics.We have built the framework with Multicube explorer andthe evaluation module with partial implementation of theparameter space. We still have to implement variable numberof cores and dynamic task to core mapping. With the smallerparameter space, we have done full search, which is taking along time (days) already, and we are currently working onsetting up a genetic algorithm traversal.IV. CONCLUTIONSIn this paper we presented our ongoing work towardsfinding appropriate multi-core architecture that meets stricttiming requirements of an application. The framework con-tributes towards ensuring all application requirements aremet, building upon automated design-space exploration andMRTA. We still need to work on covering all of parameterspace, which is only partially done so far. Also, hardwarecost analysis needs to be updated for realistic market values.We will evaluate heuristic algorithms, compare results andestablish an efficient way to achieve the architecture designfile. Future work is to integrate FPGA evaluation and synthesisinto the framework to achieve a custom application specificprocessor.REFERENCES[1] S. Altmeyer, R. I. Davis, L. Indrusiak, C. Maiza, V. Nelis, and J. Reineke,“A generic and compositional framework for multicore response timeanalysis,” in Proceedings of the 23rd International Conference on RealTime and Networks Systems, ser. RTNS ’15, 2015, pp. 129–138.[2] R. I. Davis, S. Altmeyer, L. S. Indrusiak, C. Maiza, V. Nelis,and J. Reineke, “An extensible framework for multicore responsetime analysis,” Real-Time Systems, Jul 2017. [Online]. Available:https://doi.org/10.1007/s11241-017-9285-4[3] M. Thompson, “Tools and techniques for efficient system-level designspace exploration,” Ph.D. dissertation, University of Amsterdam, 2012.[4] J. Gustafsson, A. Betts, A. Ermedahl, and B. Lisper, “The MälardalenWCET Benchmarks: Past, Present And Future,” in 10th InternationalWorkshop on Worst-Case Execution Time Analysis (WCET 2010), 2010,pp. 136–146.[5] S. Hahn, J. Reineke, and R. Wilhelm, “Towards compositionality inexecution time analysis: Definition and challenges,” SIGBED Rev.,vol. 12, no. 1, pp. 28–36, Mar. 2015.[6] C. Silvano, W. Fornaciari, G. Palermo, V. Zaccaria, F. Castro, M. Mar-tinez, S. Bocchio, R. Zafalon, P. Avasare, G. Vanmeerbeeck, C. Ykman-Couvreur, M. Wouters, C. Kavka, L. Onesti, A. Turco, U. Bondik,G. Mariani, H. Posadas, E. Villar, C. Wu, F. Dongrui, Z. Hao, andT. Shibin, “Multicube: Multi-objective design space exploration of multi-core architectures,” in 2010 IEEE Computer Society Annual Symposiumon VLSI, July 2010, pp. 488–493.[7] H. Calborean and L. Vinan, “An automatic design space explorationframework for multicore architecture optimizations,” in 9th RoEduNetIEEE International Conference, June 2010, pp. 202–207.

Work In Progress: Design-Space Exploration of Multi-core Processors for Safety-Critical Real-Time Systems

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Work In Progress: Design-Space Exploration of Multi-core Processors for Safety-Critical Real-Time Systems

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