The verification of complex digital designs often involves the use of expensive simulators.
The present paper proposes an approach to verify a specific family of complex hardware/software
systems, whose hardware part, running on an FPGA, communicates with a software counterpart
executed on an external processor, such as a user/operator software running on an external PC.
The hardware is described in VHDL and the software may be described in any computer language
that can be interpreted or compiled into a (Linux) executable file. The presented approach uses open
source tools, avoiding expensive license costs and usage restrictions.Unión Europea 68722
