International audienceDataflow models of computation are a natural intermediate representation for high-level synthesis. Many criteria must be fulfill to end up with an efficient circuit implementation, the first one being channel implementation. After scheduling the processes, it is very likely that producer/consumer communication patterns can no longer be implemented as a FIFO, causing major inefficiency in the final circuit as non-FIFO channels required additionnal synchronization circuitry and may slow-down dramatically the whole implementation.In this poster, we focus on a popular scheduling technique, the loop-tiling, widely used in automatic parallelization; and we study an algorithm to restructure the channels so the FIFOs broken by the loop tiling are restored. We exhibit a class of process networks -- the data-aware process networks -- for which the recovery is complete: after a loop tiling, all the FIFOs can always be recovered. Experimental results confirm the completeness of the recovery into the DPN class -- and measure the non-completeness outside of the DPN class
