Realization of logic integrated circuits in VeSTIC process - design, fabrication, and characterization

Abstract

A design and manufacturing of test structures for characterization of logic integrated circuits in a VeSTIC process developed in ITE, are described. Two variants of the VeSTIC processs have been described. A role and sources of the process variability have been discussed. The VeSFET I-V characteristics, the logic cell static characteristics, and waveforms of the 53-stage ring oscillator are presented. Basic parameters of the VeSFETs have been determined. The role of the process variability and of the parasitic elements introduced by the conservative circuit design, e.g. wide conductive lines connecting the devices in the circuits, have been discussed. Based on the inverter layout and on the process specification, the parasitic elements of the inverter equivalent circuit have been extracted. The inverter propagation times, the ring oscillator frequency, and their dependence on the supply bias have been determined