With the ever-increasing complexity of integrated circuits, the elimination of all design errors before fabrication is becoming more difficult. This increases the need to find design errors in chips after fabrication. This task, termed post-silicon debug, can be made easier if it is possible to obtain a trace of states that leads to a known state. BackSpace, a proposal for a new debug infrastructure which provides such a trace has been recently presented. BackSpace combines formal analysis with on-chip instrumentation. In this thesis, we show that BackSpace can be made practical by modifying the architecture and debug flow to address the area overhead, and also by addressing on-chip realities such as non-determinism and signal propagation delay. Additionally, this thesis describes a proof-of-concept implementation of a complex processor instrumented with the debug architecture and shows that BackSpace can produce traces hundreds of cycles long. Our results indicate that the area overhead of the breakpoint circuit, a main component of the debug architecture, can be reduced to 5% for our prototype, while still allowing the debug flow to create state-accurate traces.Applied Science, Faculty ofElectrical and Computer Engineering, Department ofGraduat
