Although high-level synthesis (HLS) tools have significantly improved
programmer productivity over hardware description languages, developing for
FPGAs remains tedious and error prone. Programmers must learn and implement a
large set of vendor-specific syntax, patterns, and tricks to optimize (or even
successfully compile) their applications, while dealing with ever-changing
toolflows from the FPGA vendors. We propose a new way to develop, optimize, and
compile FPGA programs. The Data-Centric parallel programming (DaCe) framework
allows applications to be defined by their dataflow and control flow through
the Stateful DataFlow multiGraph (SDFG) representation, capturing the abstract
program characteristics, and exposing a plethora of optimization opportunities.
In this work, we show how extending SDFGs with multi-level Library Nodes
incorporates both domain-specific and platform-specific optimizations into the
design flow, enabling knowledge transfer across application domains and FPGA
vendors. We present the HLS-based FPGA code generation backend of DaCe, and
show how SDFGs are code generated for either FPGA vendor, emitting efficient
HLS code that is structured and annotated to implement the desired
architecture