Domain Wall Enabled Hysteresis-Free Steep Slope Switching in MoS$_2$ Transistors

Abstract

The device concept of operating ferroelectric field effect transistors (FETs) in the negative capacitance (NC) regime offers a promising route for achieving energy-efficient logic applications that can outperform the conventional CMOS technology, while the viable mechanisms for stabilizing the NC mode remain a central topic of debate. In this work, we report hysteresis-free steep slope switching in few-layer and bilayer MoS$_2$ transistors back-gated by single layer polycrystalline PbZr$_{0.35}$Ti$_{0.65}$O$_3$ films. The devices exhibit current on/off ratios up to 8$\times$10$^6$ within an ultra-low gate voltage window of V$_g$ = $\pm$0.5 V and subthreshold swing as low as 9.7 mV/decade at room temperature, transcending the 60 mV/decade Boltzmann limit. Unlike previous studies, the quasi-static NC mode is realized in a ferroelectric without involving an additional dielectric layer. Theoretical modeling reveals the dominant role of the metastable polar states within ferroelectric domain walls in enabling the NC mode in the MoS$_2$ transistors. Our findings shed light into a new mechanism for NC operation, providing a simple yet effective material strategy for developing high speed, low-power 2D nanoelectronics.Comment: 15 pages, 5 figure