Presently, the major challenge at the device level is the lack of sufficient device power gain of commercial IC technologies at THz. In this dissertation, we will address this device-level challenge. We first characterize their THz behaviors/modeling. Then, novel circuits-aware device core designs and optimizations to boost the device-level “gain-bandwidth product” at THz are presented.
This dissertation presents a wideband power amplifier at THz frequency range. The proposed power amplifier covers the frequency range from 100 to 125 GHz, supporting the operation in the low band of the D-band. Moreover, a novel embedding network, called complex neutralization scheme, is presented to boost the power gain of the device for near-fmax operation. Furthermore, in-house automation program is presented for optimum selection of the complex neutralization embedding network. The goal of this program is to maximize device Gain-BW for the available technology at target operating frequencies.
Furthermore, the proposed power amplifier is cascaded to increase the output power along with high gain. The presented work contains 3-stage complex neutralized differential blocks with output power combiner. The matching stages are optimized for low loss and wideband operation.
The proposed power amplifier is taped-out on using GlobalFoundries 45nm FD-SOI CMOS process. The electromagnetic simulations for the proposed power amplifier, which is biased in class AB, demonstrate a small signal gain of 19dB at 115 GHz with k factor more than 17. Moreover, the large signal simulations show a peak power added efficiency of 14% with saturated output power of 12.6dBm. The proposed system has a total active area of 0.23mm².M.S