In modern communication, sensor and signal processing systems digitisation methods are gaining importance. They allow for building software configurable systems and provide better stability and reproducibility. Moreover digital front-ends cover a wider range of applications and have better performance compared with analog ones. The quest for new architectures in radio frequency front-ends is a clear consequence of the ever increasing number of different standards and the resulting task to provide a platform which covers as many standards as possible. At microwave frequencies, in particular at frequencies beyond 10 GHz, no direct sampling receivers are available yet. A look at the roadmap of the development of commercial analog-to-digital-converters (ADC) shows clearly, that they can neither be expected in near future. We present a novel architecture, which is capable of direct sampling of band-limited signals at frequencies beyond 10 GHz by means of an over-sampling technique. The wellknown Nyquist criterion states that wide-band digitisation of an RF-signal with a maximum frequency ƒ requires a minimum sampling rate of 2 · ƒ . But for a band-limited signal of bandwidth B the demands for the minimum sampling rate of the ADC relax to the value 2 · B. Employing a noise-forming sigma-delta ADC architecture even with a 1-bit-ADC a signal-to-noise ratio sufficient for many applications can be achieved. The key component of this architecture is the sample-and-hold switch. The required bandwidth of this switch must be well above 2 · ƒ . We designed, fabricated and characterized a preliminary demonstrator for the ISM-band at 2.4 GHz employing silicon Schottky diodes as a switch and SiGe-based MMICs as impedance transformers and comparators. Simulated and measured results will be presented

E. M. Biebl

J.-F. Luy

M. Streifinger

T. Müller

Advances in Radio Science

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Advances in Radio Science (2003) 1: 201–205c© Copernicus GmbH 2003 Advances inRadio ScienceA software-radio front-end for microwave applicationsM. Streifinger1, T. Müller2, J.-F. Luy2, and E. M. Biebl11Technische Universität München, Fachgebiet Ḧochstfrequenztechnik, Arcisstr. 21, 80333 München, Germany2DaimlerChrysler Forschungszentrum, Wilhelm-Runge-Str. 11, 89081 Ulm, GermanyAbstract. In modern communication, sensor and signal pro-cessing systems digitisation methods are gaining importance.They allow for building software configurable systems andprovide better stability and reproducibility. Moreover digi-tal front-ends cover a wider range of applications and havebetter performance compared with analog ones. The questfor new architectures in radio frequency front-ends is a clearconsequence of the ever increasing number of different stan-dards and the resulting task to provide a platform which cov-ers as many standards as possible.At microwave frequencies, in particular at frequencies be-yond 10 GHz, no direct sampling receivers are available yet.A look at the roadmap of the development of commercialanalog-to-digital-converters (ADC) shows clearly, that theycan neither be expected in near future.We present a novel architecture, which is capable of di-rect sampling of band-limited signals at frequencies beyond10 GHz by means of an over-sampling technique. The well-known Nyquist criterion states that wide-band digitisationof an RF-signal with a maximum frequencyf requires aminimum sampling rate of 2· f . But for a band-limitedsignal of bandwidthB the demands for the minimum sam-pling rate of the ADC relax to the value 2· B. Employinga noise-forming sigma-delta ADC architecture even with a1-bit-ADC a signal-to-noise ratio sufficient for many appli-cations can be achieved. The key component of this architec-ture is the sample-and-hold switch. The required bandwidthof this switch must be well above 2· f .We designed, fabricated and characterized a preliminarydemonstrator for the ISM-band at 2.4 GHz employing sil-icon Schottky diodes as a switch and SiGe-based MMICsas impedance transformers and comparators. Simulated andmeasured results will be presented.Correspondence to:M. Streifinger(streifinger@ei.tum.de)1 IntroductionMany applications of communication, sensor and signal pro-cessing systems would provide greater performance, if vari-ous standards could be handled with only one hardware de-vice. Conceivable applications could be combined GSM /GPS devices (M̈uller et al., 2000) or a GPS receiver com-bined with a short-range radar. One first step towards this aimis the realization of a direct sampling receiver. The advantageis, that the input frequency and the channel bandwidth can bechosen in the receiver’s digital part, fully independent of theused front-end.In the following some analogue receiver architectures andthe architecture of a direct sampling receiver will be intro-duced. The validity of the concept given and multiple simu-lations will be proved by measured results of a scaled demon-strator at 2.4 GHz.2 Multiband capable receiver architecturesThe requirements for multiband receivers lead to two mainneeds regarding the receiver topology: On the one handthe centre frequency has to be tuned over a large frequencyrange. On the other hand the bandwidths of the standards candiffer by more than two decades.The limit of heterodyne receivers regarding the tuneablebandwidth is given by the first IF frequency. Because ofthe non-linear character of the mixer, fourth order harmon-ics will arise between baseband and the double bandwidth ofthe input filter. This limits the maximum tuning bandwidthsignificantly or increases the number of IF stages up to anuneconomical number.An attractive alternative is the direct conversion receiver.As shown in the block diagram (Fig. 1) the signal is mixeddown to the baseband by two orthogonal carriers separately(Jentschel et al., 2000). This receiver can be built up veryeconomically but several drawbacks prevent the usage formultimode receivers. Because of the always existing I-Q202 M. Streifinger et al.: A software-radio front-end for microwave applications   Fig. 1. Block diagram of the direct conversion receiver.mismatch this topology is not suited for high order modu-lation schemes. A leakage of the LO leads to partly timevariant DC bias after the down converting process which arecostly to suppress. Because the bandwidth of the standardis defined by the lowpass filter, it has to be configured formultimode reception (B̈ohm et al., 1999).The problem of LO leakage can be partly solved by us-ing a very low IF for this type of receiver and implementingthe shift into the baseband in the digital domain (Crols andSteyaert, 1998).Looking at standards at mm-wave frequencies the Six-Portreceiver becomes attractive (Tatu et al., 2001). The six-portcan be considered as a black box with two inputs and fouroutputs. When the six-port itself is linear and the outputs arenon-linear the relations between input signals and the out-put signals can be derived by a calibration procedure. Thefeasible tuning bandwidth is given by the characteristics ofthe six-port itself and the subsequent non-linear devices. Thechannel bandwidth is defined by the lowpass filters behindthe non-linear outputs. A straight-forward approach to soft-ware configurable receivers is to sample the input signal atan IF or the input frequency itself. Bandpass-limited under-sampling can be used to reduce the sampling rate and theeffort in processing the digital signals. Unfortunately, the in-fluence of sampling jitter and the requirements on the antialiasing filter increases when doing this.A disadvantage of sampling at IF is, that the IF filter de-fines the maximum channel bandwidth. When choosing alarge IF bandwidth to receive any possible standard, the re-quired dynamic range increases and leads to intermodulationspecifications comparable to wide band sampling systems.Figure 2 shows the block diagram of a combined GSM– GPS receiver, where both standards are received in timemultiplex (Müller, 2002). The intermediate frequency waschosen in a way that the digital down-conversion can be real-ized by the multiplication with ones and zeros. The basebandprocessing is done by standard chipsets (Müller et al., 2000).When sampling the RF signal directly, the analog-to-digital converter has to cope the high input bandwidth andall interferers after the antenna. The immense advantage is  LOGSMBPB=2MHzBP BPΣ∆Mod.DezimationGSM-Basis-bandproz.SiemensGPS-Basis-bandproz.PlesseySystemsteuerung, Anzeige0,1,0,-11,0,-1,0BP BPGPS: 1575,42MHzGSM: 935 - 960MHzZF = 43,875MHzfs=19,5MHzLO GSM: 891-916 MHzLO GPS: 1531,56MHz LOGPS Fig. 2. Block diagram of a GSM – GPS receiver with common IF.that we obtain full flexibility in choosing the input frequency,channel bandwidth etc. by selecting the proper digital signalprocessing. The following chapter will present the design ofa 24GHz sampling head.3 Concept of a direct sampling receiverThe concept of the direct sampling receiver is based on aband limited over sampling approach. The Nyquist-criterionis applied to the bandwidth of the signal of interest ratherthan to the complete incoming spectrum. Sampling of thewhole spectrum of the input signal with a maximum fre-quencyf , the minimum sample rate would be 2· f . If thebandwidthB of the signal of interest is well known, the de-mands for the minimum sampling rate relax to the value of2 · B (Vaughan et al., 1991).In case of oversampling the oversampling ratio (OSR)is defined as ratio of half the sampling rate related to the3 dB-bandwidth of the filter. For an application in the ISMband (f0 = 24 GHz) the required bandwidth would beB =500 MHz. We assume a ratio off0 · 4fs= n = 9and obtain a sampling frequency offs = 10.66 GHz and anOSR = 10.66 in this case. The expected resolution of thisADC is 3 bit (without noise shaping).Using this concept, a noise shaping Sigma Delta Convertercan be realized which will further improve the resolution(Norsworthy et al., 1997). The expected signal to noise ratiois shown in Fig. 3.The aim is the realisation of the architecture shown inFig. 4 for an input frequency of 24 GHz. As a first step, ascaled demonstrator was built up and analysed at 2.4 GHz.The following exposition mainly handles this demonstrator.If necessary and sensible, comments regarding the feasibilityat 24 GHz will be made.The key components of the receiver are the anti aliasingfilter, the clocked sample & hold circuit (S/H) and the com-parator or ADC itself as shown in Fig. 4 (Luy and Müller,1999).M. Streifinger et al.: A software-radio front-end for microwave applications 203   Fig. 3. Reachable signal to noise ratio of a 1-bit sigma delta con-verter and converters without noise shaping dependant on the OSR.   Fig. 4. Digital millimeter wave receiver architecture.The anti-aliasing-filter (AAF) suppresses all out-of-bandinterferers in order to fulfil the Nyquist criterion at least re-garding the bandwidth of the signal of interest.The output voltage of the S/H switch must follow the in-put signal as long as the switch is closed (Fig. 6). Thus,the output impedance of the first amplifier driving the switchbridge has to be rather small. Good results are received byvalues of less then 10. For this reason an impedance trans-former is needed, as we usually have systems with a 50wave impedance. On the other hand, to hold the output volt-age of the S/H switch constant as long as the switch is open,the input impedance of the second amplifier should be morethan 200. So we need a second impedance transformer,to transform the 200 impedance back to a value dependanton the subsequent stage. Moreover both impedance trans-formers have to amplify the signals according to the dynamicrange of the respective stages.The clocked comparator and further signal processingparts are beyond the scope of this paper.The key component of the receiver is the S/H circuit asshown in Fig. 5. As sampling switch a SIMMWIC Schottkydiode quadruple bridge is used, followed by a shunt lumpedholding capacitor (Jensen and Larson, 2001). The diodes arewell suited because of their high reverse and their low for-ward resistance. As the diode switch contains four strong   Fig. 5. schematic of the sample and hold circuit.nonlinearities generating many harmonics and intermodula-tion products an precise simulation of the circuit is ratherdifficult but nonetheless absolutely essential. Generally spo-ken the diode switch is the most broad-banded component ofthe whole front-end.To prevent cross talk between the incoming signal and theclock signal, the diode quadruple has to be driven symmetri-cally. This is achieved by implementing a balun circuit in theclock signal path. Further very critical components are thelength of the wave guide between the diode switch and theholding capacitor as well as the capacitor’s physical dimen-sions. If one of them two is too large, oscillations emergebecause of the parasitic inductivities and the holding capaci-tance.4 Simulation of the sample and hold circuitHaving an exact diode model is crucial for the correct sim-ulation of the sampling circuit. The following parameterswhere extracted from DC and RF measurements: Saturatedreverse current:IS = 4,3 nA, serial resistanceRS = 8,5, ide-ality factorN = 1.09 and zero bias junction capacityCj0 =12 fF...14 fF.Simulations have shown that small changes ofIS , RS andN do not affect the behaviour of the device much, whereaseven small changes in the value ofCj0 can deteriorate thefunctionality of the switch: During the hold stage, outputvoltage shows sinusoidal oscillations. Obviously, the iso-lation between signal input and the output is not sufficientdue to the capacitive coupling by the junction capacity. As acountermeasure one can either apply a reverse DC bias or in-crease the clock power. Adding reverse DC bias increases thecomplexity of the circuit significantly, increasing the clockpower is limited by the maximum forward current of thediodes. Simulations showed that we could expect sufficientisolation for reasonable clock power without reverse bias forworking in the ISM Band at 24 GHz.Figure 6 shows the voltage measured at the holding ca-pacitor. As input signal an unmodulated carrier of 2.4 GHzwas used. The SMA connectors and bonding wires were204 M. Streifinger et al.: A software-radio front-end for microwave applications   Fig. 6. Simulated voltage time curve at the holding capacitance and state of the diode switch.   Fig. 7. Specification of the 2.4 GHz demonstrator.not considered in this simulation. As can be seen, the out-put voltage follows the input signal as long as the switch is“closed”. When the switch is open, the output voltage isnot exactly constant. In fact, decaying high-frequency os-cillations are observed. A comprehensive examination ofthis effect shows, that parasitic inductivities of the bondingwires and the via holes are responsible for that behaviour.As shown later (Fig. 9), a simulation including these para-sitics predicts very well the measured results. This indicatesthat proper models are used for the hardware components andlayout structure.5 Demonstrator at 2.4 GHzFor being able to verify the simulated results a scaled demon-strator at 2.4 GHz was built. It was realized without AAF andcomparator. Based on the results of the simulations showed,the following specifications (Fig. 7) were chosen.The demonstrator was built according to the specificationsgiven in Fig. 7 and characterized. Both impedance ampli-fiers were realized by ATMEL. To work around the prob-   Fig. 8. The chip module with both impedanc tranformers and thediode bridge.lems of the bonding wires and their parasitic influences, bothimpedance transformers were assembled on one chip wherethe diodes were also flip chip bonded on. In future, also theholding capacity will be integrated in this chip module.The chip module was mounted on TMM10i substrate andconnected to the balun and the bias circuits. The connectionsto the sources and to a sampling oscilloscope were done viaSMA connectors mounted on the demonstrator’s backside.Figure 9 shows the output voltage, measured at the holdingcapacitance. This signal corresponds well to the simulatedoutput voltage shown in Fig. 6. A problem; which has still tobe solved, are the oscillations created by the parasitics. Theyare mainly caused by the externally mounted chip capacitor.In future, it will be integrated on the chip module containingthe diode bridge and the impedance transformers.M. Streifinger et al.: A software-radio front-end for microwave applications 205   Fig. 9. Measured output voltage.6 ConclusionAn overview on existing mm-wave receivers was given. Thedirect sampling receiver based on band-limited oversamplingseems to be the best and most flexible solution, but as it isthe most ambitious approach, it still needs extensive devel-opment. The critical components have been analysed andspecified. It appears that a realisation for applications work-ing in the ISM band at 24 GHz seems possible using presenttechnologies.ReferencesBöhm, K., Pfau, J., Schnepp, H.: A tunable low power BiCMOScontinuous-Time Gm-C lowpass filter, IEEE Radio and WirelessConference, T5.6, Denver, Colorado, USA, August 1999.Crols, J. and Steyaert, M. S.: Low-IF Topologies for High-Performance Analog Front Ends of Fully Integrated Receivers,IEEE Tr. on Circuits and Systems – II: Analog and Digital Sig-nal Processing, 45, 3, 1998.Jensen, J. C. and Larson, L. E.: A Broadband 10-GHz Track-and-Hold in Si/SiGe HBT Technology, IEEE Journal of Solid StateCircuits, 36, 3, 2001.Jentschel, H.-J., Berndt, H., and Pursche, U.: Direct ConversionReceivers – Expectations and Experiences, in RF Front End Ar-chitectures, IEEE MTT-S 2000, Boston, Workshop, 2000.Luy, J. F. and M̈uller, Th.: Front-End Architectures in Millimeter-Wave Systems: From Analogue to Digital Concepts, EuMC1999, Munich, pp. 309–312, 1999.Müller, T., Biebl, E. M., B̈ohm, K., and Luy, J.-F.: Zwischen-frequenz – digitalisierender GPS / GSM Empfänger, Klein-heubacher Berichte 2000, Band 43, pp. 301–307, 2000.Müller, T.: Direktabtastende Architekturen fr Hochfrequen-zempf̈anger, Dissertation, Fachgebiet Höchstfrequenztechnik,TU München, 2002.Norsworthy, S., Schreier, R., and Temes, G.: Delta-Sigma DataConverters, Theory, Design and Simulation, IEEE Press 1997,Piscataway, NJ, 1997.Tatu, S. O., Moldovan, E., Wu, K., and Bosisio, R. G.: A New Di-rect Millimeter-Wave Six-Port Receiver,IEEE Tr. on MicrowaveTheory and Techniques, 49, 12, 2001.Vaughan, R. G., Scott, N. L., and White, D. R.: The Theory ofBandpass Sampling, IEEE Transactions on Signal Processing,39, 9, 1991.

A software-radio front-end for microwave applications

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A software-radio front-end for microwave applications

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