Silicon (Si) has a strength to density ratio of 3.0({sigma}{sub y}/{delta}=(6.8GPa/2.3g/cc)), an order-of-magnitude higher than titanium, aluminum, or stainless steel. Silicon also demonstrates favorable thermal, optical, and electrical properties making it ideal for use as a structural foundation for autonomous, mesoscopic systems such as nanosatellites. Using Si substrates, a structure that can simultaneously act as a thermal management system, a radiation shield, an optical material, a package, and a semiconductor substrate can be realized

Christenson, T.R.

Kravitz, S.H.

Shul, R.J.

Willison, C.L.

Zipperian, T.E.

UNT Digital Library

%.. ---4 54/w99”3/% L ‘Silicon Microfabrication Technologies for Nano-Satellite Applications;q@~@i ~ ~R. J. Shul, S. H. Kravitz, T. R. Christenson? C. G. Willison, and T. E. Zipperian’“&?&’44 ~+ Zgj”)Abstract o~pjSilicon (Si) has a strength to density ratio of 3.0(aY/6=(6.8Gpa/2.3g/cc)), anuorder-of-magnitude higher than titanium, aluminum, or stainless steel. Silicon alsodemonstrates favorable thermal, optical, and electrical properties making it ideal foruse as a structural foundation for autonomous, mesoscopic systems such asnanosatellites. Using Si substrates, a structure that can simultaneously act as athermal management system, a radiation shield, an optical material, a package, and asemiconductor substrate can be realized.IntroductionRecently, several semiconductor fabrication processes have been developedto en~ble the use of Si substrates as structural foundation for autonomous,mesoscopic systems. Perhaps the most important development has been a deepreactive ion etch (DRIE) process which has revolutionized the concept andimplementation of mixed technology integration. Using the. DRIE process, a Sisubstrate may be etched to specific depths with highly controlled lateral dimensions.This allows accurate alignment of dissimilar components and materials to oneanother and accurate wafer-to-wafer alignment. Utilizing on-chip microelectronicand mechanical structures, this technology will enable fabrication of a self-contained, highly versatile, integrated rnicrosystem that will minimize volume,weight, and power requirements. DRIE also enables the pursuit of a collection ofadvanced packaging capabilities to address the need for complex rnicrosystems thatcombine multiple materials and functions in a single package or assembly.Discussion and ResultsPattern transfer into Si has been very successful by both wet chemical andplasma etch techniques. However, the fabrication of deep, high-aspect ratio Sistructures has been limited due to low etch selectivity to photoresist masks, slowetch rates, or poor lateral dimensional control. The recent development of the DRIESi etch process has resulted in anisotropic profiles at room temperature, etch rates>3.0 prnhnin, aspect ratios >30:1, and good dimensional control. Additionally, DRIEhas shown etch selectivities of Si to photoresist >75:1 thereby eliminating the use ofhard etch masks for features deeper than 100 pm.The DRIE process (patented by Robert Bosch GmbH) [1] relies on aniterative inductively coupled plasma (ICP) deposition/etch cycle in which a polymer‘ Sandia National Laboratories, Albuquerque, New Mexico 87185-06031-r-7r7 . . . .?lT. -., m,mT-.T -- ,, ,. . . . ..,,>v&?Lm”s --. . . ..- -,..,.. . . -.— IDISCLAIMERThis repofl was prepared as an account of work sponsoredby an agency of the United States Government. Neither theUnited States Government nor any agency thereof, nor anyof their employees, make any warranty, express or implied,or assumes any legal liability or responsibility for theaccuracy, completeness, or usefulness of any information,apparatus, product, or process disclosed, or represents thatits use would not infringe privately owned rights. Referenceherein to any specific commercial product, process, orservice by trade name, trademark, manufacturer, orotherwise does not necessarily constitute or imply itsendorsement, recommendation, or favoring by the UnitedStates Government or any agency thereof. The views andopinions of authors expressed herein do not necessarilystate or reflect those of the United States Government orany agency thereof.DISCLAIMERPortions of this document may be illegiblein electronic image products. Images areproduced from the best available originaldocument... .—=... .—.. ..— —— -- - —. ...——— —- .. I,4. * #.etch inhibitor is conformably deposited over the wafer during the deposition cycle.The polymer deposits over the resist mask, the exposed Si field, and along thesidewall. During the ensuing etch cycle, the polymer film is preferentially sputteredfrom the Si trenches and the top of the resist mask due to the acceleration of ions(formed in the ICP plasma) perpendicular to the surface of the wafer. Provided theion scattering is relatively low, the polymer film on the sidewall is removed at amuch slower rate, thus minimizing lateral etching of the Si. Before the sidewallpolymer is completely removed, the deposition step is repeated and the cyclecontinues until the desired etch depth is obtained.Through-wafer plated vias for electrical interconnects are used in manyintegrated rnicrosystems including nano-satellites. Recently, a robust electroplatedvia technology for through-wafer interconnects has been developed using severalmicrofabrication processes. These processes included Si DRIE to form the through-wafer via holes, steam oxidation to isolate the metal via plugs from the siliconsubstrate, and electroplating to form the metal plugs. As shown in Figure la, 100pm wide vias are formed in -425 Lm thick Si using the DRIE process. Electricalisolation of the silicon substrate from the metal via plugs is achieved using steamoxidation. For high aspect ratio (>1: 1) vias, neither LPCVD nor PECVD depositionprocesses will adequately isolate the via. These processes are limited by thediffusi6n of large molecules into the via and the diffusion of reaction products out ofthe via. As a result, the deposited film thickness decreases with depth into the via.However, steam oxidation of silicon can completely insulate vias bygrowing the oxide in place, rather than depositing films onto exposed surfaces. Inthis case, only water and oxygen molecules need to enter the via while hydrogen isthe only reaction product. The oxide grown in the vias is uniform throughout theentire depth. The rate of oxidation of films over 1000 ~ thick is limited bydiffusion of water and oxygen through the existing oxide film. At one atmospherepressure, the practical limit for oxide growth is about 2 pm at 1200”C. h highpressure (25 atmospheres) oxidation systems, it is possible to grow thicker films inshorter times or to oxidize at temperatures as low as 500°C. The breakdown voltagefor steam oxidized films is about 100 volts per pm film thickness.Following oxidation, the vias are electroplated using the following process.A copper substrate is coated with polymethylmethacrylate (PMMA) photoresist andsolvent bonded to the Si wafer. The PMMA is removed in the via locations with adeep ultraviolet (DUV) blanket exposure and development cycle using the oxidizedsilicon wafer as a stencil mask. The vias are then electroformed using an electrolyticnickel deposition. Finally the copper plating fixture is completely removed in asimple wet etch process. Plated vias Me shown in Figure lb for 100 pm wide vias.A series of plated vias were tested electrically and determined to be isolated fromthe Si wafer. A similar fabrication sequence for copper and gold vias is alsopossible, as well as for nickel-iron (Permalloy) to allow the incorporation of throughwafer magnetic fl,uxpaths.Another fabrication process required for integrated Microsystems is waferbonding. There are many device applications that can benefit from joining twosilicon wafers or a silicon and Pyrex wafer. These seals could be hermetic, which2——.. —.—,(a)Figure 1. SEM micrographs of 100pmprocess and b) Ni electroplated.(b)diameter vias a) etched using the DRIEallows silicon to serve as a packaging medium as well as a device substrate. If twoor more substrates can be accurately aligned before sealing, the possibility forma.khg inexpensive and sophisticated devices from divergent technologies exists.After wafer bonding occurs, the resultant sealed devices can be diced into individualpackages.DRIE provides a process which enables accurate alignment of wafers as wellas precision die-to-wafer alignment for advanced packaging technologies. A Sisubstrate can be etched ~o multiple, specific depths while retaining accuratelycontrolled dimensions in the mask plane. This permits accurate alignment ofdiscrete components to one another with alignment tolerances c 5 pm. In Figure 2,the DRIE process was used to accurately align two Si samples to one another. A130 ym wide pin was DRIE etched in the top Si wafer while a 132 pm wide wellwas DRIE etched in the bottom Si wafer. The pins and wells were aligned and thenattached using a UV curing adhesive to tolerances of <5 pm on pieces - 10 cmz.Using a slightly different pattern, pieces as large as % of a 3 inch Si wafer have beenslimed to tolerances of-25 um.(i!) (b)Figure 2. Schematic (a) and (b) SEM micrograph or DRIE etched Si pins and wellsfor precision alignment for advanced packaging technologies.Wafers can then be bonded together using a number of different techniques.Commercially availablealignment accuracies ofwafer alignment/bonding systems are available with& 2 pm. These machines can heat to 600”C, and apply3“. $.,programmed pressure;controlled atmosphereand voltage for anodic bonding. They can also provide aor vacuum during the bonding process. Wafer bondingtechniques include: direct wafer fision, anodic bondin~, ‘frit glass bonding, solde;bonding, and adhesive bonding. In direct wafer fusion, wafers are aligned andbonded at 600”C with no additional material. The lightly bonded wafers are thentransferred to a high temperature furnace where bonding is completed at >1OOO”C.Anodic bonding relies on the formation of an oxide grown on silicon at the interfacewith Pyrex glass. A high voltage is applied to the wafer, which causes the alkalimetal ions in the Pyrex to migrate to the cathode. An oxide is formed at the siliconinterface from the applied field if oxygen is present at about 300°C. Two siliconwafers can also be joined by this technique if Pyrex is sputter deposited on one ofthe wafers. Pyrex is used because its coefficient of thermal expansion (CTE)matches silicon. Frit glass bonding uses a screened film of low melting temperatureglass to seal two wafers directly. Glasses with CTE’matched to silicon and withmelting points below 600°C are commercially available. In solder bonding thesolder pre-forms or pastes can be applied to either wafer surface. Some soldersneed fluxes to create wetting. When the wafers are heating to the solder meltingpoint, solder dams may be necessary to prevent flow into unwanted regions. Solderbonding can serve both an electrical function, as well as to attach other die to thepackage. Adhesive sealing is similar to solder bonding, but either conductive ornon-conductive material can be used. Adhesives do not make hermetic seals, butcan be water resistant.Several of these microfabrication technologies have been incorporated intothe fabrication of a planar-fabricated micro-battery for potential nano-satelliteapplications. A schematic diagram of the planar micro-battery is shown in Figure 3.A set of 4 Si wafers is used to form the structure. The two exterior wafers or Siframes are used to enclose the anode and cathode while providing support for thecircuitry. On one Si frame wafer, power management circuitry is either pre-fabricated on the wafer or attached as hybrid circuits to the wafer using the DRIEprocess to precisely locate the die. The other exterior Si frame wafer can be used tosupport photovoltaic cells that can be used to power the device. Through-waferPhotovoltaic Cell Plated viasPorousMembraneAlignmentm.—-Power Ma;gement CircuitryrmsFigure 3. Schematic diagram of a micro-battery.4. v._ _,.,wm ,,,.>$~~, ,,,-,,,~=>. :. —- . --...—- . ..—— . ..—. ---— ---———-——L- .plated vias are used to provide electrical contact from the Si frame to the anode andcathode. The two interior Si wafers are patterned using DRIE in a honeycomb cellstructure to store the battery material (see Figure 4a). As shown in Figure 3, aporous film is located between the anode and cathode wafers to prevent contact ofthe anode and cathode material and allow the flow of the electrolyte materialbetween electrodes. The four wafers are accurately aligned using through-wafer viaholes and alignment pins. Stainless steel alignment pins were press-fit into thelower frame wafer and used to aliq the upper wafers. Alignment of one Si framewafer, the anode wafer, the porous membrane thin film, and the cathode wafer areshown in Figures 4b and c. Anodic bonding will be used to form a hermeticallysealed structure. In summary, a power system using micro-fabrication technologiesmay be tailored to provide a self-contained, multi-functional structure that may beof use to the nano-satellite community.4 ..-.2 mm(a)2 mm(b)2 mm(c)Figure 4. SEM micrograph of a) honeycomb structure etched into Si -400” pm deep-.using the DRIE process, b) top, and c) side view of 3 wafer Si battery aligned usinga press-fit alignment pin.Sandia is a multiprogram laboratory operated by Sandia Corporation, a LockheedMartin Company, for the United States Department of Energy under Contract DE-AC04-94AL85000.References[1] Patent No. 5501893: Method of Anisotropically Etching Silicon. Inventors: FranzLaermer, and Andrea Schilp of Robert Bosch GmbH. Issued March 26, 1996.

Silicon microfabrication technologies for nano-satellite applications

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