A delayed increase in 1/f noise is observed for pMOS transistors showing latent radiation-induced interface-trap buildup. The latent interface traps and increased noise appear to result from the same thermally activated process, likely involving hydrogen

Fleetwood, D.M.

Johnson, M.J.

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L LATENT INTEEWACE TRAPS AND lIfNOISE IN IRRADIATED MOS DEVICES D. M. Fleetwood and M. J. Johnson Sandia National Laboratories* P. 0. Box 5800, MS 1083 Albuquerque, NM 87185-1083 USA Phone (505) 844-1825; Fax (505) 844-2991 e-mail: dmfleet@smtplink.mdl.sandia.gov 35-word Abstract A delayed increase in llf noise is observed for PMOS transistors showing latent radiation- induced interface-trap buildup. The latent interface traps and increased noise appear to result from the same thermally activated process, likely involving hydrogen. DISCLAIMER This report was prepared as an account of work sponsored by an agency of the United States Government. Neither the United States Government nor any agency thereof, nor any of their employees, makes any warranty, express or implied, or assumes any legal liability or responsi- bility for the accuracy, completeness, or usefulness of any information, apparatus, product, or process disclosed, or represents that its use would not infringe privately owned rights. Refer- ence herein to any specific commercial product, process, or service by trade name, trademark manufacturer, or otherwise does not necessarily constitute or imply its endorsement, recom- mendation, or favoring by the United States Government or any agency thereof. The views and opinions of authors expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof. * Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy under Contract DE-AC04-94AL85000. Portions of this document may be illegible in electmnic image productst h a g s  are pmciuced from tbe best available original d O ~ ~ L  Summary A strong correlation has been observed between MOS llfnoise and 0 vacancies in the Si02 gate oxide [l]. Hydrogen-related defects are also common in irra- diated MOS devices [2-61. A particularly striking effect that has been attributed to hydrogen is very long term, delayed (“latentyy) interface-trap buildup in MOS tran- sistors [6,7]. It has been proposed that latent interface- trap buildup occurs because the motion of protons re- leased during irradiation can be retarded by interactions with 0 vacancies in the SiO, [6]. If so, one might ex- pect low-frequency noise measurements to be sensitive to this hydrogen motion andor to subsequent interac- tions at or near the Si/Si02 interface. We have per- formed a detailed comparison of time-dependent net- oxide and effective interface-trap .densities with llf noise levels through irradiation and annealing for MOS transistors showing significant latent interface-trap buildup. We find a strong increase in llfnoise that pre- cedes the latent interface-trap buildup. These results suggest the increased noise may be due to defects in the near-interfacial oxide associated with the interactions of slowly transporting protons. The devices in this study were 4 pm long, 32 pm wide PMOS transistors with 50 nm gate oxides manu- factured by Oki Semiconductor, known from previous work to exhibit latent, thermally activated interface-trap buildup [7]. Radiation-induced net-oxide (ANot) and effective interface-trap (ANit) charge densities were es- timated via the subthreshold technique of Winokur et al. [8]. This method does not distinguish between the ef- fects of “true” interface traps and fast border traps on MOS transistor subthreshold stretchout [6,9]. For that reason we refer to Mit as the “effective” interface-trap charge density. Unfortunately, the Oki transistors used in this study do not have a separate substrate contact, so charge pumping techniques cannot be used to try to dis- tinguish between interface and border trap effects, as has been done in some previous studies [5,6,9]. Noise measurements were performed at room tem- perature at various gate (V’) and drain (Vd) biases with a HP 3562A Dynamic Signal Analyzer [lo]. The back- ground noise with Vd = 0 V was typically much lower than the device llfnoise, and was subtracted to obtain the excess noise Sv. The normalized noise power spec- tral density K = S y  f(yg - K,J2Vi2 [ 11, wherefis the fie- quency and V, is the threshold voltage, was obtained by averaging values between 10 and 40 Hz. For all noise measurements shown, S, - llf a, with CI FS 1.0 -+ 0.1 [l 11. Before irradiation, the value of the Hooge figure- of-merit aH = S ~ N J W ~  [= K ( E , J . ~ ~ J ( A / ~ ) ~ ,  - Y~,J-’, where N, is the number of carriers, E, is the oxide di- electric constant, t,, is the oxide thickness, A is the area, and -4 is the electronic charge] is - (1.5 k 1.0) x for these devices, a level comparable to the low noise of JFETs [1,12]. This may indicate buried-channel (i.e., bulk) conduction in these PMOS devices [12], at least before radiation exposure. After preirradiation noise measurements, the devices were exposed to Co-60 ’y-ray irradiation at Vg = 6 V and 25°C at 92 rad(Si02)/s. The devices were then subjected to various annealing treat- ments. The drain current and gate voltage were ad- justed to maintain constant V d  and Vg - K h  for noise measurements through the irradiation and annealing sequences to simplify comparisons with previous work and with noise models in the literature [ 1 , 10,12- 161. In Fig. 1 we show ANot and ANl for a PMOS Oki transistor irradiated at V, = 6 V, then annealed at vari- ous temperatures and biases. During irradiation (time t < 800 s), both ANo, and ANit increase significantly, as expected for these non-radiation-hardened devices [ 171. Through 25°C anneal at 6 V (800 s < t < 6 x lo5 s), ANot decreases logarithmically with anneal time [6,7,17]. Values of ANif fust decrease slightly after irradiation, and then increase near the end of the 25”C, 6 V anneal [6,7]. When the temperature is raised to 50°C (t - 6 x lo5 s) and higher, while maintaining 6 V bias, the de- crease in Mot accelerates with increasing anneal time and temperature. In contrast, ANit more than doubles between t = 6 x lo5 s (25°C) and t = 2 x lo6 s (100°C) before saturating, consistent with latent interface trap buildup [6,7]. When the temperature is raised to 175”C, ANit decreases dramatically due to interface-trap anneal- ing [18]. The decrease in ANit continues when the bias is switched to -6 V at 175OC, while Mot increases slightly after this bias switch [6]. Upon cooling the de- vices to 100°C and returning to 6 V bias, ANif increases slightly and Mot decreases again. In Fig. 2 we compare the normalized llfnoise and Hit through the irradiation and anneal sequence of Fig. 1. These noise measurements were performed at Vd = 0.4 V and V, - Vth = -1 V [13,14]. There is a remark- able correlation between K and ANit in Fig. 2 throughout the entire irradiation and anneal sequence, approxi- mately of the form In K - ANit. This is consistent with the observation that the noise of some PMOS power transistors correlates with ANit [ 161, but contrasts with the close link between llfnoise and oxide trap density seen in nMOS transistors [1,10,14]. However, the strong increase in K during the initial 25"C, 6 V anneal precedes the latent increase in ANit in Fig. 2 by at least 4 x lo5 s (- 4.5 days). Moreover, K increases by a factor of - 50 for times between 2 x lo5 s and 2 x lo6 s, while ANjt increases by a factor of - 2.7. This approximately exponential increase in noise with increasing defect density is not predicted by any of the standard number or mobility fluctuation models of noise in MOS transis- tors [1,13,15]. So it does not appear to be just the in- crease in ANit that causes the increased noise in these devices. However, the striking correlation between K and ANjt through the entire irradiation and anneal period in Fig. 2 certainly suggests a strong link between the processes that lead to the enhanced llfnoise and latent interface-trap buildup and annealing in these devices. In Fig. 3 we show ANot and ANit for a second group of devices irradiated to 75 krad(Si02) at 25°C and an- nealed at rt 6 V bias at 100°C. At this higher annealing temperature, both the reduction in ANot and latent buildup of ANit are accelerated [6,7]. Switching from positive to negative anneal bias increases the densities of both defect types; returning to positive bias decreases the densities of each [6]. In Fig. 4 noise measurements are compared to ANjt for this irradiation and anneal se- quence. These noise measurements were performed at Vd = 0.2 V and V, - V, = -2 V. (The specific bias conditions for the noise measurements did not affect the trends in the data, as verified by checking the response at several biases other than those reported here [l 11.) We now compare the results of Figs. 2 and 4 dur- ing the initial 6 V anneal. Similar to Fig. 2, the strong increase in K in Fig. 4 precedes the increase in ANip However, the delay between the increase in noise and ANjt is only about 4000 s 1.1 h) at 100°C in Fig. 4, compared to at least 4 x' 1 O s delay at the lower anneal- ing temperatures in Fig. 2. The overall magnitudes of the increases in noise and effective interface-trap densi- ties are otherwise similar in Figs. 2 and 4. Hence, the results of Figs. 2 and 4 strongly suggest that the latent interface-trap buildup and the increase in llfnoise in these Oki transistors are due to a single thermally acti- I- vated process. In previous work, the activation energy for latent interface-trap buildup in Oki transistors was estimated to be - 0.47 eV [lo]. The similarity of the acceleration of the noise and latent interface trap buildup rates in Figs. 2 and 4 suggest this activation energy is also appropriate for describing the increased postirradiation llfnoise in these devices. However, it is interesting that, at this lower annealing temperature, the llfnoise level in Fig. 4 decreases when the anneal bias is switched to -6 V, then increases when the bias is re- turned to 6 V [14]. This is in contrast to ANot (Fig. 3) and ANjt (Figs. 3 and 4) which show the opposite pattern when the bias is switched. This reinforces our previous point that the same process leads to the increased llf noise and latent interface-trap buildup, but neither ANol or ANit itself determines the noise level. Recently, it has been suggested that the process that leads to latent interface-trap buildup in oxides having high concentrations of 0 vacancies in the Si02 gate oxide may be similar to the process by which con- ventional interface-trap buildup occurs in irradiated MOS transistors, only slower [6]. That is, radiation ex- posure releases hydrogen related species (e.g., protons) in the Si02, which begin to drift under a positive elec- tric field to the Si/Si02 interface. In oxides with low 0 vacancy densities, protons can reach the interface in tens or hundreds of seconds, initiating the interface trap buildup process [2-61. In oxides with higher 0 vacancy densities, like these Oki transistors, the protons appear to have their transport slowed, and may even be cap- tured by shallow traps associated with the 0 vacancies [6]. Within the context of this model, the increase in llf noise in Figs. 2 and 4 may be caused in part by (1) a dramatic increase in the density of border traps andfor slow interface traps with energy levels and positions appropriate for metastably exchanging charge with the Si during the noise measurements, (2) an increase in the scattering rate associated with these defects, andfor (3) proton motion near the interface. It seems plausible that (1) and (2) would occur as protons begin to reach the near-interfacial region, capture an electron to form atomic hydrogen, with some ultimately reacting at the interface to form interface traps. The increase in noise may occur as the protons move into the near-interfacial region and begin creating new border traps [ 1,6,9], with the subsequent increase in interface traps occurring when the protons reach the interface and begin creating interface traps [2-61. The hydrogen transport process may also lead to a crossover from buried-channel to near-surface conduction in these devices [12], as hydro- gen passivates some boron dopants in the Si surface layer. During these processes, the motion of the protons themselves may also contribute to the noise. The bias switching response of the noise, especially in Fig. 4, suggests at least some of these processes are reversible, especially for moderate anneal temperatures. This will be discussed in more detail in the full paper for these and other devices showing similar effects. In conclusion, we have found that the long-term delayed increase in llf noise and latent interface-trap buildup in irradiated Oki PMOS transistors with high 0 vacancy densities are evidently caused by a common thermally activated process. The results are consistent with recent work attributing latent interface-trap buildup to retarded proton motion in oxides with high 0 vacancy density [6] .  These results suggest a significant role for hydrogen-related species not only in interface trap formation in irradiated MOS devices, but also in increasing their llfnoise. This is a potentially signifi- cant performance and reliability concern for non- radiation-hardened MOS devices exposed to ionizing radiation over long periods of time. This may also be a concern for the operation of PMOS dosimeters under positive bias, where llfnoise can limit sensitivity [19], as we will also discuss in the full paper. We thank L. C. Riewe and R. A. Loemker for technical assistance, and T. L. Meisenheimer, P. S. Wi- nokur, J. R. Schwank, M. R. Shaneyfelt, W. L. Warren, and K. Vanheusden for stimulating discussions. References [I] D. M. Fleetwood, T. L. Meisenheimer, and J. H. Scofield, “llf Noise and Radiation Effects in MOS Devices,” IEEE Trans. Electron Dev. 41, 1953 (1994); D. M. Fleetwood, W. L. War- ren, M. R. Shaneyfelt, R. A. B. Devine, and J. H. Scofield, “Enhanced MOS llfNoise due to Near-Interfacial Oxygen De- ficiency,” J. Non-Cryst. Solids 187, 199 (1995). [2] P. S. Winokur, H. E. Boesch, Jr., J. M. McGarrity, and F. B. McLean, “Two Stage Process for Buildup of Radiation Induced Interface States,” J. Appl. Phys. 50,3492 (1979). [3] J. R. Schwank, D. M. Fleetwood, P. S. Winokur, P. V. Dres- sendorfer, D. C. Turpin, and D. T. Sanders, “The Role of Hy- drogen in Radiation Induced Defect Formation in Poly-Si Gate CMOS Devices,” IEEE Trans. Nucl. Sci. 34, 1152 (1987). [4] N. S. Saks and D. B. Brown, “Interface Trap Formation Via the Two-Stage Hydrogen Process,” IEEE Trans. Nucl. Sci. 36, 1848 (1989). [5] R. E. Stahlbush, A. H. Edwards, D. L. Griscom, and B. Mrstik, “Postirradiation Cracking of H, and Formation of Interface States in Irradiated MOSFETs,” J. Appl. Phys. 73,658 (1993). [6] D. M. Fleetwood, W. L. Warren, J. R. Schwank, P. S. Winokur, M. R. Shaneyfelt, and L. C. Riewe, “Effects of Interface Traps and Border Traps on MOS Postirradiation Annealing Re- sponse,” IEEE Trans. Nucl. Sci. 42, 1698 (1995). [7] J. R. Schwank, D. M. Fleetwood, M. R. Shaneyfelt, P. S. Wi- nokur, “Latent Thermally-Activated Interface-Trap Generation in MOS Devices,” IEEE Electron Dev. Lett. 13, 203 (1992); J. R. Schwank, D. M. Fleetwood, M. R. Shaneyfelt, P. S. Wi- nokur, C. L. Axness, and L. C. Riewe, “Latent Interface-Trap Buildup and Its Implications for Hardness Assurance,” IEEE Trans. Nucl. Sci. 39, 1953 (1992). [SI P. S. Winokur, J. R. Schwank, P. J. Mcwhorter, P. V. Dressen- dorfer, and D. C. Turpin, “Correlating the Radiation Response of MOS Capacitors and Transistors,” IEEE Trans. Nucl. Sci. 31, 1453 (1984). [9] D. M. Fleetwood, “Fast and Slow Border Traps in MOS De- vices,” IEEE Trans. Nucl. Sci. 43, 779 (1996); D. M. Fleet- wood, P. S. Winokur, R. A. Reber, Jr., T. L. Meisenheimer, J. R. Schwank, M. R. Shaneyfelt, and L. C. Riewe, “Effects of Oxide, Interface, and Border Traps on MOS Devices,” J. Appl. Phys. 73,5058 (1993). [lo] T. L. Meisenheimer and D. M. Fleetwood, “Effect of Radiation- Induced Charge on 1lfNoise in MOS Devices,” IEEE Trans. Nucl. Sci. 37, 1696 (1990). [l I] M. J. Johnson and D. M. Fleetwood, “Correlation Between Latent Interface Trap Buildup and 1lfNoise in MOS Transis- tors,” Appl. Phys. Lett. (accepted for publication, March 1997), is an initial brief report that is extended here. [12] L. K. J. Vandamme, X. Li, and D. Rigaud, “1lfNoise in MOS Devices: Number or Mobility Fluctuations?” IEEE Trans. Electron Dev. 41, 1936 (1994). [13] J. H. Scofield, N. Borland, and D. M. Fleetwood, “Reconciliation of Different Gate-Voltage Dependencies of llf Noise in nMOS and PMOS Transistors,” IEEE Trans. Electron Dev. 41, 1946 (1994). E141 T. L. Meisenheimer, D. M. Fleetwood, M. R. Shaneyfelt, and L. C. Riewe, “1lfNoise in n and PMOS Devices Through Irradia- tion and Annealing,” IEEE Trans. Nucl. Sci. 38, 1297 (1991). [15] K. K. Hung, P. K. Ho, C. Hu, and Y. C. Cheng, “A Unified Model for the Flicker Noise in MOSFETs,” IEEE Trans. Elec- tron Dev. 37,654 (1990). [16] P. Augier, J. L. Todsen, D. Zupac, R. D. Schrimpf, K. F. Gal- loway, and J. A. Babcock, “Comparison of 1lfNoise in Irradi- ated Power MOSFETs Measured in the Linear and Saturation Regimes,” IEEE Trans. Nucl. Sci. 39,2012 (1992). [17] P. S. Winokur, F. W. Sexton, J. R. Schwank, D. M. Fleetwood, P. V. Dressendorfer, T. F. Wrobel, and D. Turpin, “Total-Dose Radiation and Annealing Studies: Implications for Hardness Assurance Testing,” IEEE Trans. Nucl. Sci. 33, 1343 (1986). [ 181 D. M. Fleetwood, F. V. Thome, S. S. Tsao, P. V. Dressendorfer, V. J. Dandini, and J. R. Schwank, “High-Temperature SO1 Electronics for a Space Nuclear Power System: Requirements and Feasibility,” IEEE Trans. Nucl. Sci. 35, 1099 (1988). [19] N. G. Tarr, C. Plett, A. Yeaton, G. F. Mackay, and I. Thomson, “Limitations on MOSFET Dosimeter Resolution Imposed by IlfNoise,” IEEE Trans. Nucl. Sci. 43,2492 (1996). I /  n N E 0 - 1012 103 104 105 Time (5) 1 06 107 1011 Fig. 1: Net oxide-trap (solid symbols) and effective interface-trap (open symbols) charge densities for PMOS Oki transistors with 50 nm oxides irradiated at 25°C to 25, 50, and 75 krad(Si0;) at Vg = 6 V (diamonds), and then annealed at k 6 V bias for various times and temperatures. Fig. 3: Net oxide-trap (solid symbols) and effective interface-trw (open symbols) charge densities for PMOS Oki transistors with 50 nm oxides irradiated at 25OC to 75 krad(Si0J at Vg = 6 V, and then annealed at 100°C at f 6 V bias. Time (s) 10' 1 1 6  104 le 106 Time (s) Fig. 2: K normalized to its level immediately after 75 krad(SiO3 irradiation (left hand scale, solid symbols) and effective interface- trap densities (right hand scale, open symbols) for the irradiation and anneal sequence of Fig. 1. For reference, the value of K was 8.4 x V2 before irradiation, and was 3.4 x 10''' Vz after irradiation to 75 krad(SiO3, but before anneal. Fig. 4: K normalized to its level immediately after 75 krad(SiO3 irradiation (left hand scale, solid symbols) and effective interface- trap densities (right hand scale, open symbols) for the irradiation and anneal sequence of Fig. 3. For reference, the value of K was 4.2 x IO-" V2 before irradiation, and was 3.2 x 10'" V2 after irradiation to 75 krad(Si03, but before anneal. 

Latent interface traps and 1/f noise in irradiated MOS devices

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Latent interface traps and 1/f noise in irradiated MOS devices

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