A new application using atomic force microscopy (AFM) for in-line process control monitoring (PCM) of an interlevel dielectric via etching step is reported. The AFM with its near atomic-level resolution is capable of nondestructively measuring whether micron-sized vias have been etched to completion. Etch completion is determined by comparing the AFM measured etch depth of adjacent via holes through {approximately}4000 {Angstrom} thick Si{sub 3}N{sub 4} over Au-based ohmic and W gate metallizations. Due to etch selectivity, of the SF{sub 6}/0{sub 2} reactive ion etch (RIIE) generated plasma, the ohmic metal acts as an etch stop whereas the W-based refractory gate continues to etch. For etch times beyond endpoint in the range of 20 to 50%, the AFM measured via etch depth differences is 250 to 400 {Angstrom} when comparing via depths over ohmic metal and W gate metal. This etch depth difference is a specific marker for etch completion and it is measured nondestructively at a point in the process where rework is still a feasible option

Baca, A. G.

Howard, A. J.

Shul, R. J.

UNT Digital Library

- ~ .A Non-Destructive Interlevel Dielectric Via In-Line Process Monitoring by Atomic Force Microscopy A.J. Howard, A.G. Baca, and R.J. Shul Sandia National Laboratories Center for Compound Semiconductor Technology Albuquerque, NM 87I85-0603 Abstract A new application using atomic force microscopy (AFM) for in-line process control monitoring (PCM) of an interlevel dielectric via etching step is reported. The AFM with its near atomic-level resolution is capable of non-destructively measuring whether micron-sized vias have been etched to completion. Etch completion is determined by comparing the AFM measured etch depth of adjacent via holes through -4OOO 8, thick Si3N4 over Au-based ohmic and W gate metallizations. Due to etch selectivity, of the SFd02 reactive ion etch (R.IE) generated plasma, the ohmic metal acts as an etch stop whereas the W- based refractory gate continues to etch. For etch times beyond endpoint in the range of 20 to 50%, the AFM measured via etch depth differences is 250 to 400 8, when comparing via depths over, ohmic metal and W gate metal. This etch depth difference' is a specific marker for etch completion and it is measured non-destructively at a point in the process where rework is still a feasible option. Introduction During the processing sequence for digital integrated circuits such as a GaAs-based complementary heterostructure field-effect transistors (CHFETs) [ 11 , numerous situations exist where an in-line, non- destructive, PCM step is required. Traditional characterization techniques such as SEM and optical microscopy are either destructive or not capable of resolving micron-sized features. . The example to be presented in this paper is the development and utility of an interlevel dielectric via etch process characterization step €or a multilevel metal interconnect. Underetched via holes lead to "opens" between the interconnect metal and underlying ohmic or gate metal pads due to Si3N4 left in the via. Using surface profdometry measurements on larger area etched features for process monitoring is an option but, the results can be misleading due to microloading effects (differing etch rates for small and large area features) and etchant transport effects (etchant is less efficient getting into small diameter deep features) which are common in RE. PCM of the via etch was previously characterized using destructive cross- sectional SEM analysis. The atomic force microscope (AFM) [2] is capable of directly measuring the etch depth for micron-sized features. In this paper we will report a new AFM-based characterization technique for a interlevel dielectric via process which operates in an in-line, non-destructive fashion. This technique will be an important yield-enhancing tool for IC manufacturing. 1 Results and Discussion The GaAs-based FET fabrication steps relevant to this work are as follows: (1 thick W .film and RIE; (2) Ohmic metal definition with -3000 8, of GeAuNiAu; (3) Interlevel dielectric deposition using -4000 8, of Si3N4; and (4) Fabrication of 1.25 pm via holes defined by optical lithography'and etched in a R E  SFg/@ generated plasma. Endpoint is determined during the plasma etch using in-situ optical interferometry on large open areas. If the via hole resist mask is even slightly underexposed or underdeveloped, resist may remain in the via resulting in an incomplete etch and cause an "open" in the circuit. Optical inspection of individual 1.25 pm via holes cannot Refractory gate definition with a 3000 A DISTRIBUTION OF THIS DBCUMEPJT IS UNLI$A/IIVED $ 5  DISCLAIMER This report was prepared as an account of work sponsored by an agency of the United States Government. Neither the United States Government nor any agency thereof, nor any of their employees, make any warranty, express or implied, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any information, apparatus, product, or process disclosed, or represents that its use would not infringe privately owned rights. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise does mot necessarily constitute or imply its endorsement, recommendation, or favoring by the United States Government or any agency thereof. The views and opinions of authors expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof. DISCLAIMER Portions of this document may be illegible in electronic image products. Images are produced from the best available original document. I , .. distinguish between vias with resist scum and those without. Using Dektak measurements on larger etched features is an option but, the results can be misleading due to RIE-associated microloading and transport effects, and differences in Si3N4 thickness of larger areas and small areas over metal. SEM analysis has also been unsuccessful unless operated in the destructive cross section mode. Via etch rates and etch depths can also be determined by destructive and time consuming SEM analysis on sacrificial devices. This technique works for characterizing a process but is unsuitable for in-line process monitoring. Because of the destructive nature and limitations with other characterization techniques, development of in in-line, non- destructive AFM-based analysis method for the interlevel dielectric via etch process was investigated. An AFM image of five etched Si3N4 via holes over two ohmic Au-based metal pads and a W gate metal pad (a refractory gate FET) is shown in Figure 1. These images are geaerated by performing tapping mode AFM on a Digital Instruments, Dimension 3000 AFM system in a normal cleanroom environment after the via patterning step is completed. SEM images similar to this AFM image can be obtained non-destructively, but, 3-D digital height data is not available with SEM. Using the measured 3-D AFM data, the images are analyzed in cross section by taking line traces through the vias. Etch depths of 4018 8, and 3993 8, are measured for the vias in Figure 2. These values are copelated to previously recorded Si3N4 thickness values which were measured by ellipsometry. Using the AFM, we have determined that the deposited Si3N4 thickness on top of the metal ohmic and gate pads is 85 35% of the thickness measured optically over larger field areas. The optically measured field area thickness was also confirmed by performing AFM measurements on larger etched areas. For this sample, the average Si3N4 thickness in the field was 4450 %, which correlates to a Si3N4 thickness on metal pads of 3782 %, based on 85% thickness variation. Comparing the 3782 %, value to the AFM measured via etch depths of 4018 %, and 3993 A, we conclude that the vias are etched to completion. Although this technique has measurement uncertainties on the order of 35% which limit its ability to detect if the last 100 to 200 8, of Si3N4 are removed, it is a significant improvement in detecting non- destructively, unopened vias. In order to identify a more highly controlled process control monitor using the AFM, vias were etched from 20 to 150% of endpoint. AFM characterization of the vias were evaluated over ohmic and gate metal for etch depth, RMS surface roughnesses, and via dimension. RMS surface roughness and via dimensions showed virtually no effect as a. function of etch time. However, comparing the etch depth for vias over Au- based ohmic and W-gate metals as a function of etch time showed a difference as the vias were overetched. The etch depth for vias over the ohmic metal remained essentially unchanged whereas the etch depth over gate metal continued to increase due to the poor selectivity of Si3N4 over W in this plasma chemistry. Therefore an etch marker for completion was identified. In Figure 3 the AFM measured etch depth for the vias over the gate and ohmic metals are. plotted as a function of etch time. More significantlx, the difierence in measured etch depth between the gate and ohmic bqied vias are also plotted in Figure 3. The via depth over the Au-based ohmic metal reaches a maximum value, whereas, ' the via depth over the W metallization continues to increase. The F-based plasma etch chemistry used to etch the Si3N4 attacks the W gate once the Si3N4 is cleared but does not etch the Au-based ohmic. The amount of W removed during the Si3Nq etch was quantified by removing the Si3N4 overlayer with buffered oxide etchant (BOE) and then re-measuring by AFM. The selectivity of Si3N4 over W in BOE was quite high with virtually no loss of W. An AFM image of the 50% overetched sample is shown in Figure 4. The circular depression in the W gate and the lack of these features in the adjacent Au-based ... ohmics represents the via chemistry selectively etching the W, this region of the W gate is exposed during the via overetch. This depression was measured by AFM to be 450 k 50 A; this equates to an etch rate of W in the SF6/@ plasma of 690 &min (the Si3N4 etch rate is 3000 &in). The AFM measured depression depth and the previously measured gate - ohmic via depth difference are both plotted in Figure 5 as a function of percentage of endpoint. As expected, there is good agreement between these independently measured results. This difference in measured etch depth on adjacent via holes over ohmic and W metals is a non-destructive marker of via etch completion. The via process typically includes a 20% overetch to account for uncertainties in endpoint, microloading effects, Si3N4 thickness non-uniformities, and etch non-uniformity. With this specific process marker, we conclude that the vias are etched to completion as long as a 200 - 500 8, via etch depth difference (see Figure 5) is measured on adjacent gate- and ohmic- based vias by AFM,. Consequently, this in- line process check has been added to our - GaAs IC fabrication sequence. Conclusions Using AFM we have developed an in-line non-destructive PCM technique for an interlevel dielectric via etch process. This technique relies on the difference in etch rate for Au-based and W-based metallization when exposed to the R E  generated SFg/02 plasma used to dry etch the Si3N4 interlevel dielectric. During the 20% overetch the underlying .Au-ohmic and W-gate metal pads are exposed to plasma when the via clears. During the overetch portion of the via process, Au is not noticeably etched whereas the W is etched at a rate of 690 A/min to a depth of 250 to 300 A; an etch depth difference easily detectable by AFM. Hence if an etch depth difference less than -100 is measured on adjacent gate- and ohmic-based vias, we conclude that fhe vias are underetched and the process limits have been exceeded. This process inspection technique is now routinely used in-line during CHFET fabrication in our laboratory. We have found that by performing this type of AFM characterization in-line, we can conclusively identify failures at a point in the process where rework is still a feasible option. Acknowledgments The authors would like to thank L. Griego and A.T. Ongstad for their expert technical assistance with this project. This work performed at Sandia National Laboratories is supported by the U.S. Department of Energy under contract DE-AC04-94AL85000. References [l] A.G. Baca, J.C. Zolper, M.E. Sherwin, P.J. Robertson, R.J. Shul, A.J. Howard, D.J. Rieger, ahd J.F. Klem, GaAs IC Symposium Tech. Digest, p. 59-62 (1994). [2] G. Binnig, C.F. Quate, and C. Gerber, Phys. Rev. Lett., 56,930-933 (1986). Figul‘e 1. AFM image of 1.25 pm via holes etched in Si3N4 which is covering a W gate and two ohmic pads. I Figure 2. Cross-sectional analysis method for determining via etch depth. The cursor placement yields via depths of 4018 A and 3993 A. .. Figure 3. AFh4 image of the 150% etched sample after the Si3N4 was chemically removed. Note the depression in the W gate and lack thereof in the ohmics. 5 0 0  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5 0  g h cc E +Ohmic  5 200  5 5 - 1 0  0 f 1 0 0  0 . . . ' . . . ' . . - ,  . . . . . . . .  0 2 0  4 0  6 0  8 0  1 0 0 1 2 0 1 4 0 1 6 0  Etch Time (% of Endpoint) Figure 4. Plot showing the AFM measured via etch depth over ohmic and gate metallizations as a function of etch time. The second plot is of the measured via depth over gate minus the via depth over ohmic: the difference increases due to W plasma attack during overetch. 5 0  . . . . . . . . . . . . . . . . . . .  b a t e - O h m i c  Delta 0 4 0  8 0  1 2 0  1 6 0  200 Etch Time ("A of Endpoint) Figure 5. A comparison between the AFM measured via depth over gate minus via depth over ohmic difference and the measured etched depth into the W gate metal (after Si3N4 removal) as a function of etch time. J 

Non-Destructive Inter-Level Dielectric via in-Line Process Monitoring by Atomic Force Microscopy

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Non-Destructive Inter-Level Dielectric via in-Line Process Monitoring by Atomic Force Microscopy

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