A smart pixel detector is being developed for Time Resolved Crystallography for biological and material science applications. Using the Pixel detector presented here, the Laue method will enable the study of the evolution of structural changes that occur within the protein as a function of time. The x-ray pixellated detector is assembled to the integrated circuit through a bump bonding process. Within a pixel size of 150 x 150 {mu}m{sup 2}, a low noise preamplifier-shaper, a discriminator, a 3 bit counter and the readout logic are integrated. The readout, based on the Column Architecture principle, will accept hit rates above 5x10{sup 8}/cm{sup 2}/s with a maximum hit rate per pixel of 1 MHz. This detector will allow time resolved Laue crystallography to be performed in a frameless operation mode, without dead time. Target specifications, architecture, and preliminary results on the 8 x 8 front-end prototype and column readout are presented

Beuville, E.

Cork, C.

Earnest, T.

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4 c h Lawrence Berkeley Laboratory e UNIVERSITY OF CALIFORNIA Accelerator & Fusion Research Division Presented at the APS Meeting, Argonne, IL, October 16-20, 1995, and to be published in the Proceedings REC El V ED A 2D Smart Pixel Detector for Time-Resolved Protein Crystallography E. Beuville, C. Cork, T. Earnest, W. Mar, J. Millaud, D. Nygren, H. Padmore, B. Turko, G. Zizka, P. Date, and N.-H. Xuong October 1995 JUN 19 O S T I  C ~ ~ Y ~ ~ ~ ~ T ~ ~ ~  OF THlS ~~~~~~ ~ IS ~ ~~~,~ ~  Prepared for the U.S. Department of Energy under Contract Number DE-AC03-76SF00098 DISCLAIMER This document was prepared as an account of work sponsored by the United States Government. While this document is believed to contain correct information, neither the United States Government nor any agency thereof, nor The Regents of the University of California, nor any of their employees, makes any warranty, express or implied. or assumes any legal responsibility for the accuracy, completeness, or usefulness of any information, apparatus, product, or process disclosed, or represents that its use would not infringe privately owned rights. Reference herein to any specific commercial product, process, or service by its trade name, trademark, manufacturer, or otherwise, does not necessarily constitute or imply its endorsement, recommendation, or favoring by the United States Government or any agency thereof, or The Regents of the University of California. The views and opinions of authors expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof, or The Regents of the University of California. This report has been reproduced directly from the best available copy. Ernest Orlando Lawrence Berkeley National Laboratory is an equal opportunity employer. t LBL-37542 LSBL-297 uc-400 A 2D Smart Pixel Detector for Time-Resolved Protein Crystallography E. Beuville, C. Cork, T. Earnest, W. Mar, J. Millaud, D. Nygren, H. Padmore, B. Turko, and G. Zizka Accelerator and Fusion Research Division Ernest Orlando Lawrence Berkeley National Laboratory University of California Berkeley, California 94720 P. Datte and Nguyen-Huu Xuong University of California, San Diego La Jolla, California 92093 October 1995 This work was supported by the Laboratory Directed Research and Development Program of the Ernest Orlando Lawrence Berkeley National Laboratory under the US. Department of Energy, Contract No. DE-ACO3- 76SF00098. MASTER A 2D Smart Pixel Detector for Time ResoIved Protein CrystaIIography E.Beuville, C.Cork, T.Earnest, W. Mar7 J.Millaud, D-Nygren, H.Padmore, B.Turko, G.Zizka Lawrence Berkeley National Laboratory, University of California, Berkeley, CA 94720 RDatte, Nguyen-Huu Xuong University of California San Diego Abstract A smart pixel detector is Wing developed for T i e  Resolved Crystallography for biological and material science applications. Using the Pixel Detector presented here, the h u e  method will enable the study of the evolution of structural changes that occur withiin the protein as a function of time. The x-ray pixellatea detector is assembled to the interned circuit through a bump bonding process. Within a pixel size of 1 5 O ~ l S ~ ~ ,  a low noise preamplifier-shaper, a discriminator, a 3 bit counter and the readout Iogic are integrated The read out, based on the Column Architecture principle, will accept hit rites above Sx108/cm2/s with a maximum hit rate per pixel of 1MHz. This detector will allow time resolved Laue crystal- lography to be performed in a fhmeless operation mode, with- out dead time. Target specifications, architecture and p r e l i m i  results on the 8x8 frontad prototype and the col- umn readout are presented. L INTRODUCI'ION X-ray detection for protein crystallogmphy experiments has been relying on energy integrating media (films) or frame based imaging devices (imaging plates, phosphor screefls cou- pled to Charge Coupled Devices -CCDs). These detectors offer excellent spatial resolution but the h e  needed to read them out is prohibitively long for time resolved aystdognphy. Phosphor screens with CCDs &out cmrently being intro- duced as the next genention of energy integrating devices still have read out time on the order of one second. Smart Pixel h y s  Detectors offer substantial improve- ments when compared with existing devices. In particular fra- meless readouts will enable two or three orders of magnitude in time resolution improvement for time resolved crystallography. Originally these detectors were pursued at Lawrence Berkeley National Laboratory by the High Energy Physics community in relation to its experimentd needs in charged particle tracking at low ndii, high luminosity particle colliders. Smart Pixel Amy Detectors consist of monolithic m y s  of reverse b e  semiconductor diodes hybridized with an Application Specific Integrated Circuit (ASIC) instrumenting each diode in the m y .  Incident X-mys, through direct energy conversion, are absorbed in the pixels where hey create elec- trodhole pairs. When the photon is totally converted in a pixel, the number of pairs is proportional to its energy. The electronic signal generated can be processed on an event basis or inte- gxated over a period of time on many events. Smartness resides entireIy in the capability of the signal processor and readout structure. Event driven smart pixel m y  detectors based on the Column Architecture CUI provide multiparameter information (energy and time), with sparse and frameless readout, without drxd'time [l]. Low end, energy integrating smart pixels offer substantial speed advantage when compared to CCDs and an unique advantages for time resolved or static h u e  protein crystallography and are likely to open new insights into the molecular processes. The silicon diode m y  is bump-bonded to the integrated circuit configuring a module (fig.1). The column based archi- tecture allows the IC's output pads to be on one side of the module which will make easier the assembly of the whole detection area The readout electronics architecture is shown in Figure 2 The individual pixel processor consists of a low-noise amplifier shaper foliowed by a comparator which provides the counting of individual photons with an energy above a programmable e n e y  threshold To accommodate the very high rates, above 5.10 /cm2/s, each pixel processor has a 3 bit pre-scaler which divides the event rate by 8. Overflow from the divider which defines a pseudo fourth bit will generate a readout sequence where the pixeI's address is readout. The pixel address is con- verted off-chip and used to increment a loution in an histo- gnmming memory to generate the computerized image of the h u e  diagmn. x-ray 1 ReadoutBoard / Fig. 1: Smvt pixcl module 1 F i g 2  Electronics architecture preamp's RESET Equivdent Noise Charge (RMS) An 8x8 ANALOG PIXEL PROTOTYPE lqls 80011s 5%- 646 An 8x8 analog pixel prototype has been integrated in the HP 0 . 8 ~  3 metal process available through MOSIS. This first prototype contains only the analog f rontad Cmtegmtor- &per) that will alIw us to check the connectivity of the bump bonding process as well as to characterize different detector materid to be used (Silicon, CdZnTe). CdZnTe pixeIs with identical geometxy ~IE being developed by U.C. San Diego in association with DIGIRAD (San Diego, CA). The third metal layer has been only used in the layout as a ground plane to shield the electronics from the detector and to prevent any coupling from the digital .Y. circuitry to the inputs. vp vxm VI. Figs: Integrator schematic @% circuit not shown) m jf-1 , py: n.4 Lz Fig.4: Shapcr schcmatic (bias circuit not shown) . -  . .- figure 3 shows the schematic of the ascoded low-noise integntor optimized for 03pF detector capacitor. The DC reset is provided by the transistor M m  with the external control voltage V R ~  An on-chip photodiode has been integrated (gated by transistor Mswc) to allow optical test on the m y .  The preamplifier is coupled to the shaper (fig. 4) using the gate oxide capacitor of a MOS transistor (C,jpO.2pm for the dif- ferentiation stage. A MOS transistor (MwI), b m d  in its hear region by MRI and ME, is used to implement the feedback resistor of the shper amplifier. The shaping time constant can be adjusted with Vw and the shper bias current, from 50ns to 150ns. The smdl dynamic range ensure a relatively good linearity of the shaping [2]. The integrator and shper output pulses me shown in fig- ure 5. The total gain is 860mV/fC (or 140mV/1000e-). The noise meamxed without any detectors connected at the input is 52eRhIS which should rise up to 1lOe- with the silicon diode connected at the input (Cdet+CpaN;t;c-03pr;). The over- all power consumption is less than SOuW/channeI (V=-3V). F i g 5  Integrator and shper output Table 1: ENC for different preamp's reset (no detector) The fast reset of the integrator has only a small effect on the noise pedormance and allows an infinite dynamic range. The shper's baseline is kept consmt which wouId have not been the case for longer m e t  time constants due to the difkr- entiat ion. 2 In a later prototype, the compmtor will be DC coupled to the pmp-shapcr  to achieve the energy discrimination (threshold will be set around 3.6keV or loOOe-). In order to get a good threshold adjustment, the DC output voltage should be reproduced from pixel to pixel. The measurements of the 8x8 mays over 17 chips have shown that the standard deviation of the shper's output voltage is mund  o 4 m V  which corre- spond to 57e- (the expected value, as interpolated from Upel-. gxum et al. [3], was around 5mV). Fig.6: F&t integrator reset for high counting me (input step voltage going through 10fF equivalent to 2ooOe injected) Iv. ~LUMNREADOUTPROTCYRPE A prototype of the pre-scaler and the readout logic has been integrated and tested. The pre-scaler is a 3 bit counter dividing the event rate by 8. When a pixel has accumul;lted 8 counts, the overflow bit (the pseudo fourth bit) is sent to the end of the column via the DAm-READY line (fig.7). The end of the coIumn generates then a synchronization signal SYNC to prevent any overwriting of the overflows whiIe the pre-sul- us are counting and the readout sequence starts. The ripple logic, common to 2 columns, sends the overllowing pixel's addtess, ADRL and ADRH, to the end of the column where they are formatted and forwarded to the data acquisition logic. These addresses are analog currents generated at the pixel level The conversion of the addresses will be done externally. When a pixel address readout is completed, the end-of+ol- umn logic sends an endsf-read signal (EOR) and pn>cesses another overflowing pixel, if any. Each pixel readout cycle takes approximately Sons. The readout sequence ends when the end-af-colwnn receives the ENAOUT of the ripple logic. When the aquisition has stopped a read remainder cycle (fig.8) allows to get the contents of the pre-scalers. A masking logic has also been implemented to turn off any undesirable pixel. Every signal going through the column is a current signaI which means that the associated voltage on the line is less than 0.8Volts for a better speed and lower power consumption. The information generated by the detectors assemblies consists of the pixel address within the detector system. Dual columns of 100 pixels opentc indepcndcntly and in pmllcl to accommo- 3 The histogramming memory DSP (HSP48410 histognm- mer/accumulating buffer) is configured to operate in the asyn- chronous mode where each address points to a 24 bit Fegister (counter) yielding to 3 10 bit x 24 bit memory.unit. The 10 bit pixel address from the column encoder is sampled and the associated pixel's 24 bit register is incremented. PCP address Address ?raasferGain Shaping time constant ENC for C,p 0 pF (measured) ENC for C e  03pF (expected) Power Consumption ( V w p  3 V) Sustainable average event rate Sustainable peak rate per pixel L Addrrss 860 mV/K loo I1s 64e-rms 120 e- rms 50 pW S x W  an% (10OWpixel) 1- Fig 9: Column encoder addressing scheme VI. HYBRIDIZATIONTECHNOLOGY Chip hybridization technology as well as wafer level tech- nologies have been investigated for prototypes and production. At the chip level gold bumps and conductive thermoplastic a?? affonhble and proven for bumps no less than 50p'in diame- ta. They are aIso effective at the wafer/module level hence offer an effective to transition the development from a proto- type to a module. Assemblies are being made at ETEC (Pea- body, MA) Using conductive thermoplastic. This process has the advantage of being low temperatme, low pressure and thus less likely to damage the ASIC or the detector particularly in the case of CdZnTe where surface damage can lead to a sub- stantial increase of surhcecurrent. Wafer level processes (solder bumps, indium bumps) can- not be easily or cheaply adapted to the chip level bumping but very effective for mass production quantities. However sol- der cannot be used with CdZnTe due to the high temperature VII. LAYOUT IBpired. The 2 main blocs of the electronics have d m d y  been h t e  grated. Figure 10 shows the actual layout of the complete pixel mdout (analog frontad and the digital readout) within ISOxlS0pm2. Analog and digital Circuits will have in&pen- dent supplies. 150x150 pn' Fig.10 Floor plan of the complete pixel 4 Vm. CONCLUSIONS Time resolved h u e  crystallography will be performed in a fiameless opention mode without dead time. The dual-col- umns opem independently regrouping in the final prototype 100 pixels. Acquisition and nxdout are done concurrently allowing a mtainable event rate of 5x108/cm2/s (1OOkHZ avmge/pixel). The fast reset capability of the integrator accommodates a sustainable peak rate/piixel of I Mhz with an infinite dynamic range. The pixel masking upabdity will allow to turn off defective pixeIs in any desired pattern- The column architecture gives the possibfity to abut modules on 3 sides for large arrays, and these into larger elements. A full 50x50 array willbe constructed. This will bethe basic ASIC for a complete system. These building blocks will be combined into 2x2 mays modules. IX. ACKNOWIEDGMENTS We would like to thank CRossington and J.Walton from This work was supported by the Laboratory Directed LBNL for fabricating the silicon pixel detectors, R e s m h  and Development program. x. m a s  [I] J.Millaud and D.Nygm, The column architecture - a ' novel architecm for event driven 2D pixel imagers", to be published in the IEEE Nucl. Sciences Symposium, San- Francisco, 1995 (21 EBeuVille, WHeam and CVu, "A low noise amplifier- shaper with tail correction for the nuclear detector STAR", to be published in the IEEE Nuel. Sciences Symposium, (31 UPelgrom, ADuinmaijer and AWelbers, "Matching Properties of MOS Tdstors",  IEEE J. Solid-state Cir- cuits, ~0124, nos, ~1433,1989. [4] B.Turko, EBeuville, J.MilIaud and H.Yaver, "AD pro- cessing system for 64element pixel detector", ro be pub- lished in the IEEE Nucl. Sciences Symposium, Sm- Francisco, 1995. S~UI-FGIIIC~SCO, 1995 

A 2D smart pixel detector for time-resolved protein crystallography

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